1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Display Clock & Reset Controller for SM8450
8
9 maintainers:
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12 description: |
13 Qualcomm display clock control module provides the clocks, resets and power
14 domains on SM8450.
15
16 See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
17
18 properties:
19 compatible:
20 enum:
21 - qcom,sm8450-dispcc
22
23 clocks:
24 minItems: 3
25 items:
26 - description: Board XO source
27 - description: Board Always On XO source
28 - description: Display's AHB clock
29 - description: sleep clock
30 - description: Byte clock from DSI PHY0
31 - description: Pixel clock from DSI PHY0
32 - description: Byte clock from DSI PHY1
33 - description: Pixel clock from DSI PHY1
34 - description: Link clock from DP PHY0
35 - description: VCO DIV clock from DP PHY0
36 - description: Link clock from DP PHY1
37 - description: VCO DIV clock from DP PHY1
38 - description: Link clock from DP PHY2
39 - description: VCO DIV clock from DP PHY2
40 - description: Link clock from DP PHY3
41 - description: VCO DIV clock from DP PHY3
42
43 power-domains:
44 description:
45 A phandle and PM domain specifier for the MMCX power domain.
46 maxItems: 1
47
48 required-opps:
49 description:
50 A phandle to an OPP node describing required MMCX performance point.
51 maxItems: 1
52
53 required:
54 - compatible
55 - clocks
56 - '#power-domain-cells'
57
58 allOf:
59 - $ref: qcom,gcc.yaml#
60
61 unevaluatedProperties: false
62
63 examples:
64 - |
65 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
66 #include <dt-bindings/clock/qcom,rpmh.h>
67 #include <dt-bindings/power/qcom,rpmhpd.h>
68 clock-controller@af00000 {
69 compatible = "qcom,sm8450-dispcc";
70 reg = <0x0af00000 0x10000>;
71 clocks = <&rpmhcc RPMH_CXO_CLK>,
72 <&rpmhcc RPMH_CXO_CLK_A>,
73 <&gcc GCC_DISP_AHB_CLK>,
74 <&sleep_clk>,
75 <&dsi0_phy 0>,
76 <&dsi0_phy 1>,
77 <&dsi1_phy 0>,
78 <&dsi1_phy 1>;
79 #clock-cells = <1>;
80 #reset-cells = <1>;
81 #power-domain-cells = <1>;
82 power-domains = <&rpmhpd RPMHPD_MMCX>;
83 required-opps = <&rpmhpd_opp_low_svs>;
84 };
85 ...
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