1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 %YAML 1.2 3 --- 4 $id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 7 title: Qualcomm Global Clock & Reset Controller on SM8650 8 9 maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 12 description: | 13 Qualcomm global clock control module provides the clocks, resets and power 14 domains on SM8650 15 16 See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h 17 18 properties: 19 compatible: 20 const: qcom,sm8650-gcc 21 22 clocks: 23 items: 24 - description: Board XO source 25 - description: Board Always On XO source 26 - description: Sleep clock source 27 - description: PCIE 0 Pipe clock source 28 - description: PCIE 1 Pipe clock source 29 - description: PCIE 1 Phy Auxiliary clock source 30 - description: UFS Phy Rx symbol 0 clock source 31 - description: UFS Phy Rx symbol 1 clock source 32 - description: UFS Phy Tx symbol 0 clock source 33 - description: USB3 Phy wrapper pipe clock source 34 35 required: 36 - compatible 37 - clocks 38 - '#power-domain-cells' 39 40 allOf: 41 - $ref: qcom,gcc.yaml# 42 43 unevaluatedProperties: false 44 45 examples: 46 - | 47 #include <dt-bindings/clock/qcom,rpmh.h> 48 clock-controller@100000 { 49 compatible = "qcom,sm8650-gcc"; 50 reg = <0x00100000 0x001f4200>; 51 clocks = <&rpmhcc RPMH_CXO_CLK>, 52 <&rpmhcc RPMH_CXO_CLK_A>, 53 <&sleep_clk>, 54 <&pcie0_phy>, 55 <&pcie1_phy>, 56 <&pcie_1_phy_aux_clk>, 57 <&ufs_mem_phy 0>, 58 <&ufs_mem_phy 1>, 59 <&ufs_mem_phy 2>, 60 <&usb_1_qmpphy>; 61 #clock-cells = <1>; 62 #reset-cells = <1>; 63 #power-domain-cells = <1>; 64 }; 65 66 ...
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