1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
8
9 maintainers:
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11
12 description:
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
14 organized in groups of up to 32 gates.
15
16 This device tree binding describes a single 32 gate clocks group per node.
17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
18 and the clock index in the group, from 0 to 31.
19
20 properties:
21 compatible:
22 items:
23 - enum:
24 - renesas,r7s72100-mstp-clocks # RZ/A1
25 - renesas,r8a73a4-mstp-clocks # R-Mobile APE6
26 - renesas,r8a7740-mstp-clocks # R-Mobile A1
27 - renesas,r8a7778-mstp-clocks # R-Car M1
28 - renesas,r8a7779-mstp-clocks # R-Car H1
29 - renesas,sh73a0-mstp-clocks # SH-Mobile AG5
30 - const: renesas,cpg-mstp-clocks
31
32 reg:
33 minItems: 1
34 items:
35 - description: Module Stop Control Register (MSTPCR)
36 - description: Module Stop Status Register (MSTPSR)
37
38 clocks:
39 minItems: 1
40 maxItems: 32
41
42 '#clock-cells':
43 const: 1
44
45 clock-indices:
46 minItems: 1
47 maxItems: 32
48
49 clock-output-names:
50 minItems: 1
51 maxItems: 32
52
53 required:
54 - compatible
55 - reg
56 - clocks
57 - '#clock-cells'
58 - clock-indices
59 - clock-output-names
60
61 additionalProperties: false
62
63 examples:
64 - |
65 #include <dt-bindings/clock/r8a73a4-clock.h>
66 mstp2_clks: mstp2_clks@e6150138 {
67 compatible = "renesas,r8a73a4-mstp-clocks",
68 "renesas,cpg-mstp-clocks";
69 reg = <0xe6150138 4>, <0xe6150040 4>;
70 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
71 <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
72 #clock-cells = <1>;
73 clock-indices = <
74 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
75 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
76 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
77 R8A73A4_CLK_DMAC
78 >;
79 clock-output-names =
80 "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",
81 "dmac";
82 };
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