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Linux/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml

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  1 # SPDX-License-Identifier: GPL-2.0
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
  8 
  9 maintainers:
 10   - Elaine Zhang <zhangqing@rock-chips.com>
 11   - Heiko Stuebner <heiko@sntech.de>
 12 
 13 description: |
 14   The RK3188/RK3066 clock controller generates and supplies clocks to various
 15   controllers within the SoC and also implements a reset controller for SoC
 16   peripherals.
 17   Each clock is assigned an identifier and client nodes can use this identifier
 18   to specify the clock which they consume. All available clocks are defined as
 19   preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
 20   dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
 21   Similar macros exist for the reset sources in these files.
 22   There are several clocks that are generated outside the SoC. It is expected
 23   that they are defined using standard clock bindings with following
 24   clock-output-names:
 25     - "xin24m"    - crystal input                 - required
 26     - "xin32k"    - RTC clock                     - optional
 27     - "xin27m"    - 27mhz crystal input on RK3066 - optional
 28     - "ext_hsadc" - external HSADC clock          - optional
 29     - "ext_cif0"  - external camera clock         - optional
 30     - "ext_rmii"  - external RMII clock           - optional
 31     - "ext_jtag"  - external JTAG clock           - optional
 32 
 33 properties:
 34   compatible:
 35     enum:
 36       - rockchip,rk3066a-cru
 37       - rockchip,rk3188-cru
 38       - rockchip,rk3188a-cru
 39 
 40   reg:
 41     maxItems: 1
 42 
 43   "#clock-cells":
 44     const: 1
 45 
 46   "#reset-cells":
 47     const: 1
 48 
 49   clocks:
 50     maxItems: 1
 51 
 52   clock-names:
 53     const: xin24m
 54 
 55   rockchip,grf:
 56     $ref: /schemas/types.yaml#/definitions/phandle
 57     description:
 58       Phandle to the syscon managing the "general register files" (GRF),
 59       if missing pll rates are not changeable, due to the missing pll
 60       lock status.
 61 
 62 required:
 63   - compatible
 64   - reg
 65   - "#clock-cells"
 66   - "#reset-cells"
 67 
 68 additionalProperties: false
 69 
 70 examples:
 71   - |
 72     cru: clock-controller@20000000 {
 73       compatible = "rockchip,rk3188-cru";
 74       reg = <0x20000000 0x1000>;
 75       rockchip,grf = <&grf>;
 76       #clock-cells = <1>;
 77       #reset-cells = <1>;
 78     };

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