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Linux/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Rockchip RK3228 Clock and Reset Unit (CRU)
  8 
  9 maintainers:
 10   - Elaine Zhang <zhangqing@rock-chips.com>
 11   - Heiko Stuebner <heiko@sntech.de>
 12 
 13 description: |
 14   The RK3228 clock controller generates and supplies clocks to various
 15   controllers within the SoC and also implements a reset controller for SoC
 16   peripherals.
 17   Each clock is assigned an identifier and client nodes can use this identifier
 18   to specify the clock which they consume. All available clocks are defined as
 19   preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
 20   used in device tree sources. Similar macros exist for the reset sources in
 21   these files.
 22   There are several clocks that are generated outside the SoC. It is expected
 23   that they are defined using standard clock bindings with following
 24   clock-output-names:
 25     - "xin24m"      - crystal input                          - required
 26     - "ext_i2s"     - external I2S clock                     - optional
 27     - "ext_gmac"    - external GMAC clock                    - optional
 28     - "ext_hsadc"   - external HSADC clock                   - optional
 29     - "phy_50m_out" - output clock of the pll in the mac phy
 30 
 31 properties:
 32   compatible:
 33     enum:
 34       - rockchip,rk3228-cru
 35 
 36   reg:
 37     maxItems: 1
 38 
 39   "#clock-cells":
 40     const: 1
 41 
 42   "#reset-cells":
 43     const: 1
 44 
 45   clocks:
 46     maxItems: 1
 47 
 48   clock-names:
 49     const: xin24m
 50 
 51   rockchip,grf:
 52     $ref: /schemas/types.yaml#/definitions/phandle
 53     description:
 54       Phandle to the syscon managing the "general register files" (GRF),
 55       if missing pll rates are not changeable, due to the missing pll
 56       lock status.
 57 
 58 required:
 59   - compatible
 60   - reg
 61   - "#clock-cells"
 62   - "#reset-cells"
 63 
 64 additionalProperties: false
 65 
 66 examples:
 67   - |
 68     cru: clock-controller@20000000 {
 69       compatible = "rockchip,rk3228-cru";
 70       reg = <0x20000000 0x1000>;
 71       rockchip,grf = <&grf>;
 72       #clock-cells = <1>;
 73       #reset-cells = <1>;
 74     };

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