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Linux/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Rockchip RK3399 Clock and Reset Unit
  8 
  9 maintainers:
 10   - Elaine Zhang <zhangqing@rock-chips.com>
 11   - Heiko Stuebner <heiko@sntech.de>
 12 
 13 description: |
 14   The RK3399 clock controller generates and supplies clock to various
 15   controllers within the SoC and also implements a reset controller for SoC
 16   peripherals.
 17   Each clock is assigned an identifier and client nodes can use this identifier
 18   to specify the clock which they consume. All available clocks are defined as
 19   preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
 20   used in device tree sources. Similar macros exist for the reset sources in
 21   these files.
 22   There are several clocks that are generated outside the SoC. It is expected
 23   that they are defined using standard clock bindings with following
 24   clock-output-names:
 25     - "xin24m"           - crystal input                          - required,
 26     - "xin32k"           - rtc clock                              - optional,
 27     - "clkin_gmac"       - external GMAC clock                    - optional,
 28     - "clkin_i2s"        - external I2S clock                     - optional,
 29     - "pclkin_cif"       - external ISP clock                     - optional,
 30     - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
 31     - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
 32 
 33 properties:
 34   compatible:
 35     enum:
 36       - rockchip,rk3399-pmucru
 37       - rockchip,rk3399-cru
 38 
 39   reg:
 40     maxItems: 1
 41 
 42   "#clock-cells":
 43     const: 1
 44 
 45   "#reset-cells":
 46     const: 1
 47 
 48   clocks:
 49     maxItems: 1
 50 
 51   clock-names:
 52     const: xin24m
 53 
 54   rockchip,grf:
 55     $ref: /schemas/types.yaml#/definitions/phandle
 56     description:
 57       Phandle to the syscon managing the "general register files". It is used
 58       for GRF muxes, if missing any muxes present in the GRF will not be
 59       available.
 60 
 61 required:
 62   - compatible
 63   - reg
 64   - "#clock-cells"
 65   - "#reset-cells"
 66 
 67 additionalProperties: false
 68 
 69 examples:
 70   - |
 71     pmucru: clock-controller@ff750000 {
 72       compatible = "rockchip,rk3399-pmucru";
 73       reg = <0xff750000 0x1000>;
 74       #clock-cells = <1>;
 75       #reset-cells = <1>;
 76     };
 77   - |
 78     cru: clock-controller@ff760000 {
 79       compatible = "rockchip,rk3399-cru";
 80       reg = <0xff760000 0x1000>;
 81       #clock-cells = <1>;
 82       #reset-cells = <1>;
 83     };

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