1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Sophgo SG2042 PLL Clock Generator
8
9 maintainers:
10 - Chen Wang <unicorn_wang@outlook.com>
11
12 properties:
13 compatible:
14 const: sophgo,sg2042-pll
15
16 reg:
17 maxItems: 1
18
19 clocks:
20 items:
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
24
25 clock-names:
26 items:
27 - const: cgi_main
28 - const: cgi_dpll0
29 - const: cgi_dpll1
30
31 '#clock-cells':
32 const: 1
33 description:
34 See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
35
36 required:
37 - compatible
38 - reg
39 - clocks
40 - clock-names
41 - '#clock-cells'
42
43 additionalProperties: false
44
45 examples:
46 - |
47 clock-controller@10000000 {
48 compatible = "sophgo,sg2042-pll";
49 reg = <0x10000000 0x10000>;
50 clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
51 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
52 #clock-cells = <1>;
53 };
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