1 Binding for a type of flexgen structure found on certain
2 STMicroelectronics consumer electronics SoC devices
3
4 This structure includes:
5 - a clock cross bar (represented by a mux element)
6 - a pre and final dividers (represented by a divider and gate elements)
7
8 Flexgen structure is a part of Clockgen[1].
9
10 Please find an example below:
11
12 Clockgen block diagram
13 -------------------------------------------------------------------
14 | Flexgen structure |
15 | --------------------------------------------- |
16 | | ------- -------- -------- | |
17 clk_sysin | | | | | | | | |
18 ---|-----------------|-->| | | | | | | |
19 | | | | | | | | | | |
20 | | ------- | | | |Pre | |Final | | |
21 | | |PLL0 | | | | |Dividers| |Dividers| | |
22 | |->| | | | | | x32 | | x32 | | |
23 | | | odf_0|----|-->| | | | | | | |
24 | | | | | | | | | | | | |
25 | | | | | | | | | | | | |
26 | | | | | | | | | | | | |
27 | | | | | | | | | | | | |
28 | | ------- | | | | | | | | |
29 | | | | | | | | | | |
30 | | ------- | | Clock | | | | | | |
31 | | |PLL1 | | | | | | | | | |
32 | |->| | | | Cross | | | | | | |
33 | | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
34 | | | | | | Bar |====>| |====>| |===|=========>
35 | | | | | | | | | | | | |
36 | | | | | | | | | | | | |
37 | | | | | | | | | | | | |
38 | | ------- | | | | | | | | |
39 | | | | | | | | | | |
40 | | ------- | | | | | | | | |
41 | | |QUADFS | | | | | | | | | |
42 | |->| ch0|----|-->| | | | | | | |
43 | | | | | | | | | | | |
44 | | ch1|----|-->| | | | | | | |
45 | | | | | | | | | | | |
46 | | ch2|----|-->| | | DIV | | DIV | | |
47 | | | | | | | 1 to | | 1 to | | |
48 | | ch3|----|-->| | | 1024 | | 64 | | |
49 | ------- | | | | | | | | |
50 | | ------- -------- -------- | |
51 | -------------------------------------------- |
52 | |
53 -------------------------------------------------------------------
54
55 This binding uses the common clock binding[2].
56
57 [1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
58 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
59
60 Required properties:
61 - compatible : shall be:
62 "st,flexgen"
63 "st,flexgen-audio", "st,flexgen" (enable clock propagation on parent for
64 audio use case)
65 "st,flexgen-video", "st,flexgen" (enable clock propagation on parent
66 and activate synchronous mode)
67 "st,flexgen-stih407-a0"
68 "st,flexgen-stih410-a0"
69 "st,flexgen-stih407-c0"
70 "st,flexgen-stih410-c0"
71 "st,flexgen-stih418-c0"
72 "st,flexgen-stih407-d0"
73 "st,flexgen-stih410-d0"
74 "st,flexgen-stih407-d2"
75 "st,flexgen-stih418-d2"
76 "st,flexgen-stih407-d3"
77
78 - #clock-cells : from common clock binding; shall be set to 1 (multiple clock
79 outputs).
80
81 - clocks : must be set to the parent's phandle. it could be output clocks of
82 a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
83
84 - clock-output-names : List of strings used to name the clock outputs.
85
86 Example:
87
88 clk_s_c0_flexgen: clk-s-c0-flexgen {
89
90 #clock-cells = <1>;
91 compatible = "st,flexgen";
92
93 clocks = <&clk_s_c0_pll0 0>,
94 <&clk_s_c0_pll1 0>,
95 <&clk_s_c0_quadfs 0>,
96 <&clk_s_c0_quadfs 1>,
97 <&clk_s_c0_quadfs 2>,
98 <&clk_s_c0_quadfs 3>,
99 <&clk_sysin>;
100
101 clock-output-names = "clk-icn-gpu",
102 "clk-fdma",
103 "clk-nand",
104 "clk-hva",
105 "clk-proc-stfe",
106 "clk-proc-tp",
107 "clk-rx-icn-dmu",
108 "clk-rx-icn-hva",
109 "clk-icn-cpu",
110 "clk-tx-icn-dmu",
111 "clk-mmc-0",
112 "clk-mmc-1",
113 "clk-jpegdec",
114 "clk-ext2fa9",
115 "clk-ic-bdisp-0",
116 "clk-ic-bdisp-1",
117 "clk-pp-dmu",
118 "clk-vid-dmu",
119 "clk-dss-lpc",
120 "clk-st231-aud-0",
121 "clk-st231-gp-1",
122 "clk-st231-dmu",
123 "clk-icn-lmi",
124 "clk-tx-icn-disp-1",
125 "clk-icn-sbc",
126 "clk-stfe-frc2",
127 "clk-eth-phy",
128 "clk-eth-ref-phyclk",
129 "clk-flash-promip",
130 "clk-main-disp",
131 "clk-aux-disp",
132 "clk-compo-dvp";
133 };
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