1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: StarFive JH7110 System-Top-Group Clock and Reset Generator
8
9 maintainers:
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11
12 properties:
13 compatible:
14 const: starfive,jh7110-stgcrg
15
16 reg:
17 maxItems: 1
18
19 clocks:
20 items:
21 - description: Main Oscillator (24 MHz)
22 - description: HIFI4 core
23 - description: STG AXI/AHB
24 - description: USB (125 MHz)
25 - description: CPU Bus
26 - description: HIFI4 Axi
27 - description: NOC STG Bus
28 - description: APB Bus
29
30 clock-names:
31 items:
32 - const: osc
33 - const: hifi4_core
34 - const: stg_axiahb
35 - const: usb_125m
36 - const: cpu_bus
37 - const: hifi4_axi
38 - const: nocstg_bus
39 - const: apb_bus
40
41 '#clock-cells':
42 const: 1
43 description:
44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
45
46 '#reset-cells':
47 const: 1
48 description:
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
50
51 required:
52 - compatible
53 - reg
54 - clocks
55 - clock-names
56 - '#clock-cells'
57 - '#reset-cells'
58
59 additionalProperties: false
60
61 examples:
62 - |
63 #include <dt-bindings/clock/starfive,jh7110-crg.h>
64
65 stgcrg: clock-controller@10230000 {
66 compatible = "starfive,jh7110-stgcrg";
67 reg = <0x10230000 0x10000>;
68 clocks = <&osc>,
69 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
70 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
71 <&syscrg JH7110_SYSCLK_USB_125M>,
72 <&syscrg JH7110_SYSCLK_CPU_BUS>,
73 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
74 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
75 <&syscrg JH7110_SYSCLK_APB_BUS>;
76 clock-names = "osc", "hifi4_core",
77 "stg_axiahb", "usb_125m",
78 "cpu_bus", "hifi4_axi",
79 "nocstg_bus", "apb_bus";
80 #clock-cells = <1>;
81 #reset-cells = <1>;
82 };
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