1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
8
9 maintainers:
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11
12 properties:
13 compatible:
14 const: starfive,jh7110-voutcrg
15
16 reg:
17 maxItems: 1
18
19 clocks:
20 items:
21 - description: Vout Top core
22 - description: Vout Top Ahb
23 - description: Vout Top Axi
24 - description: Vout Top HDMI MCLK
25 - description: I2STX0 BCLK
26 - description: external HDMI pixel
27
28 clock-names:
29 items:
30 - const: vout_src
31 - const: vout_top_ahb
32 - const: vout_top_axi
33 - const: vout_top_hdmitx0_mclk
34 - const: i2stx0_bclk
35 - const: hdmitx0_pixelclk
36
37 resets:
38 maxItems: 1
39 description: Vout Top core
40
41 '#clock-cells':
42 const: 1
43 description:
44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
45
46 '#reset-cells':
47 const: 1
48 description:
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
50
51 power-domains:
52 maxItems: 1
53 description:
54 Vout domain power
55
56 required:
57 - compatible
58 - reg
59 - clocks
60 - clock-names
61 - resets
62 - '#clock-cells'
63 - '#reset-cells'
64 - power-domains
65
66 additionalProperties: false
67
68 examples:
69 - |
70 #include <dt-bindings/clock/starfive,jh7110-crg.h>
71 #include <dt-bindings/power/starfive,jh7110-pmu.h>
72 #include <dt-bindings/reset/starfive,jh7110-crg.h>
73
74 voutcrg: clock-controller@295C0000 {
75 compatible = "starfive,jh7110-voutcrg";
76 reg = <0x295C0000 0x10000>;
77 clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
78 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
79 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
80 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
81 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
82 <&hdmitx0_pixelclk>;
83 clock-names = "vout_src", "vout_top_ahb",
84 "vout_top_axi", "vout_top_hdmitx0_mclk",
85 "i2stx0_bclk", "hdmitx0_pixelclk";
86 resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
87 #clock-cells = <1>;
88 #reset-cells = <1>;
89 power-domains = <&pwrc JH7110_PD_VOUT>;
90 };
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