1 Binding for Texas Instruments APLL clock.
2
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped APLL with usually two selectable input clocks
5 (reference clock and bypass clock), with analog phase locked
6 loop logic for multiplying the input clock to a desired output
7 clock. This clock also typically supports different operation
8 modes (locked, low power stop etc.) APLL mostly behaves like
9 a subtype of a DPLL [2], although a simplified one at that.
10
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 [2] Documentation/devicetree/bindings/clock/ti/dpll.txt
13
14 Required properties:
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
19 It contains the information of registers in the following order:
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
22 "autoidle" - contains the autoidle register offset (OMAP2 only)
23 - ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
24 - ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
25 - ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
26
27 Examples:
28 apll_pcie_ck: apll_pcie_ck {
29 #clock-cells = <0>;
30 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
31 reg = <0x021c>, <0x0220>;
32 compatible = "ti,dra7-apll-clock";
33 };
34
35 apll96_ck: apll96_ck {
36 #clock-cells = <0>;
37 compatible = "ti,omap2-apll-clock";
38 clocks = <&sys_ck>;
39 ti,bit-shift = <2>;
40 ti,idlest-shift = <8>;
41 ti,clock-frequency = <96000000>;
42 reg = <0x0500>, <0x0530>, <0x0520>;
43 };
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