1 Device Tree Clock bindings for APM X-Gene
2
3 This binding uses the common clock binding[1].
4
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7 Required properties:
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
15
16 Required properties for SoC or PCP PLL clocks:
17 - reg : shall be the physical PLL register address for the pll clock.
18 - clocks : shall be the input parent clock phandle for the clock. This should
19 be the reference clock.
20 - #clock-cells : shall be set to 1.
21 - clock-output-names : shall be the name of the PLL referenced by derive
22 clock.
23 Optional properties for PLL clocks:
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
25
26 Required properties for PMD clocks:
27 - reg : shall be the physical register address for the pmd clock.
28 - clocks : shall be the input parent clock phandle for the clock.
29 - #clock-cells : shall be set to 1.
30 - clock-output-names : shall be the name of the clock referenced by derive
31 clock.
32 Optional properties for PLL clocks:
33 - clock-names : shall be the name of the clock. If missing, use the device name.
34
35 Required properties for device clocks:
36 - reg : shall be a list of address and length pairs describing the CSR
37 reset and/or the divider. Either may be omitted, but at least
38 one must be present.
39 - reg-names : shall be a string list describing the reg resource. This
40 may include "csr-reg" and/or "div-reg". If this property
41 is not present, the reg property is assumed to describe
42 only "csr-reg".
43 - clocks : shall be the input parent clock phandle for the clock.
44 - #clock-cells : shall be set to 1.
45 - clock-output-names : shall be the name of the device referenced.
46 Optional properties for device clocks:
47 - clock-names : shall be the name of the device clock. If missing, use the
48 device name.
49 - csr-offset : Offset to the CSR reset register from the reset address base.
50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
52 - enable-offset : Offset to the enable register from the reset address base.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
55 - divider-offset : Offset to the divider CSR register from the divider base.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
59
60 For example:
61
62 pcppll: pcppll@17000100 {
63 compatible = "apm,xgene-pcppll-clock";
64 #clock-cells = <1>;
65 clocks = <&refclk 0>;
66 clock-names = "pcppll";
67 reg = <0x0 0x17000100 0x0 0x1000>;
68 clock-output-names = "pcppll";
69 type = <0>;
70 };
71
72 pmd0clk: pmd0clk@7e200200 {
73 compatible = "apm,xgene-pmd-clock";
74 #clock-cells = <1>;
75 clocks = <&pmdpll 0>;
76 reg = <0x0 0x7e200200 0x0 0x10>;
77 clock-output-names = "pmd0clk";
78 };
79
80 socpll: socpll@17000120 {
81 compatible = "apm,xgene-socpll-clock";
82 #clock-cells = <1>;
83 clocks = <&refclk 0>;
84 clock-names = "socpll";
85 reg = <0x0 0x17000120 0x0 0x1000>;
86 clock-output-names = "socpll";
87 type = <1>;
88 };
89
90 qmlclk: qmlclk {
91 compatible = "apm,xgene-device-clock";
92 #clock-cells = <1>;
93 clocks = <&socplldiv2 0>;
94 clock-names = "qmlclk";
95 reg = <0x0 0x1703C000 0x0 0x1000>;
96 reg-name = "csr-reg";
97 clock-output-names = "qmlclk";
98 };
99
100 ethclk: ethclk {
101 compatible = "apm,xgene-device-clock";
102 #clock-cells = <1>;
103 clocks = <&socplldiv2 0>;
104 clock-names = "ethclk";
105 reg = <0x0 0x17000000 0x0 0x1000>;
106 reg-names = "div-reg";
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
110 clock-output-names = "ethclk";
111 };
112
113 apbclk: apbclk {
114 compatible = "apm,xgene-device-clock";
115 #clock-cells = <1>;
116 clocks = <&ahbclk 0>;
117 clock-names = "apbclk";
118 reg = <0x0 0x1F2AC000 0x0 0x1000
119 0x0 0x1F2AC000 0x0 0x1000>;
120 reg-names = "csr-reg", "div-reg";
121 csr-offset = <0x0>;
122 csr-mask = <0x200>;
123 enable-offset = <0x8>;
124 enable-mask = <0x200>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
128 flags = <0x8>;
129 clock-output-names = "apbclk";
130 };
131
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