1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Freescale i.MX8qm/qxp Display Pixel Link
8
9 maintainers:
10 - Liu Ying <victor.liu@nxp.com>
11
12 description: |
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
15 camera module) and pixel consumers(imaging or displays).
16 It consists of two distinct functions, a pixel transfer function and a
17 control interface. Multiple pixel channels can exist per one control channel.
18 This binding documentation is only for pixel links whose pixel sources are
19 display controllers.
20
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
22 firmware.
23
24 properties:
25 compatible:
26 enum:
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
29
30 fsl,dc-id:
31 $ref: /schemas/types.yaml#/definitions/uint8
32 description: |
33 u8 value representing the display controller index that the pixel link
34 connects to.
35
36 fsl,dc-stream-id:
37 $ref: /schemas/types.yaml#/definitions/uint8
38 description: |
39 u8 value representing the display controller stream index that the pixel
40 link connects to.
41 enum: [0, 1]
42
43 ports:
44 $ref: /schemas/graph.yaml#/properties/ports
45
46 properties:
47 port@0:
48 $ref: /schemas/graph.yaml#/properties/port
49 description: The pixel link input port node from upstream video source.
50
51 patternProperties:
52 "^port@[1-4]$":
53 $ref: /schemas/graph.yaml#/properties/port
54 description: The pixel link output port node to downstream bridge.
55
56 required:
57 - port@0
58 - port@1
59 - port@2
60 - port@3
61 - port@4
62
63 allOf:
64 - if:
65 properties:
66 compatible:
67 contains:
68 const: fsl,imx8qxp-dc-pixel-link
69 then:
70 properties:
71 fsl,dc-id:
72 const: 0
73
74 - if:
75 properties:
76 compatible:
77 contains:
78 const: fsl,imx8qm-dc-pixel-link
79 then:
80 properties:
81 fsl,dc-id:
82 enum: [0, 1]
83
84 required:
85 - compatible
86 - fsl,dc-id
87 - fsl,dc-stream-id
88 - ports
89
90 additionalProperties: false
91
92 examples:
93 - |
94 dc0-pixel-link0 {
95 compatible = "fsl,imx8qxp-dc-pixel-link";
96 fsl,dc-id = /bits/ 8 <0>;
97 fsl,dc-stream-id = /bits/ 8 <0>;
98
99 ports {
100 #address-cells = <1>;
101 #size-cells = <0>;
102
103 /* from dc0 pixel combiner channel0 */
104 port@0 {
105 reg = <0>;
106
107 dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
108 remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
109 };
110 };
111
112 /* to PXL2DPIs in MIPI/LVDS combo subsystems */
113 port@1 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 reg = <1>;
117
118 dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
119 reg = <0>;
120 remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
121 };
122
123 dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
124 reg = <1>;
125 remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
126 };
127 };
128
129 /* unused */
130 port@2 {
131 reg = <2>;
132 };
133
134 /* unused */
135 port@3 {
136 reg = <3>;
137 };
138
139 /* to imaging subsystem */
140 port@4 {
141 reg = <4>;
142 };
143 };
144 };
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