1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Freescale i.MX8MP HDMI Parallel Video Interface
8
9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de>
11
12 description:
13 The HDMI parallel video interface is a timing and sync generator block in the
14 i.MX8MP SoC, that sits between the video source and the HDMI TX controller.
15
16 properties:
17 compatible:
18 const: fsl,imx8mp-hdmi-pvi
19
20 reg:
21 maxItems: 1
22
23 interrupts:
24 maxItems: 1
25
26 power-domains:
27 maxItems: 1
28
29 ports:
30 $ref: /schemas/graph.yaml#/properties/ports
31
32 properties:
33 port@0:
34 $ref: /schemas/graph.yaml#/properties/port
35 description: Input from the LCDIF controller.
36
37 port@1:
38 $ref: /schemas/graph.yaml#/properties/port
39 description: Output to the HDMI TX controller.
40
41 required:
42 - port@0
43 - port@1
44
45 required:
46 - compatible
47 - reg
48 - interrupts
49 - power-domains
50 - ports
51
52 additionalProperties: false
53
54 examples:
55 - |
56 #include <dt-bindings/interrupt-controller/irq.h>
57 #include <dt-bindings/power/imx8mp-power.h>
58
59 display-bridge@32fc4000 {
60 compatible = "fsl,imx8mp-hdmi-pvi";
61 reg = <0x32fc4000 0x44>;
62 interrupt-parent = <&irqsteer_hdmi>;
63 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
64 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
65
66 ports {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 port@0 {
71 reg = <0>;
72 pvi_from_lcdif3: endpoint {
73 remote-endpoint = <&lcdif3_to_pvi>;
74 };
75 };
76
77 port@1 {
78 reg = <1>;
79 pvi_to_hdmi_tx: endpoint {
80 remote-endpoint = <&hdmi_tx_from_pvi>;
81 };
82 };
83 };
84 };
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