1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Mediatek display dither processor
8
9 maintainers:
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12
13 description: |
14 Mediatek display dither processor, namely DITHER, works by approximating
15 unavailable colors with available colors and by mixing and matching available
16 colors to mimic unavailable ones.
17 DITHER device node must be siblings to the central MMSYS_CONFIG node.
18 For a description of the MMSYS_CONFIG binding, see
19 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
20 for details.
21
22 properties:
23 compatible:
24 oneOf:
25 - enum:
26 - mediatek,mt8183-disp-dither
27 - items:
28 - enum:
29 - mediatek,mt8186-disp-dither
30 - mediatek,mt8188-disp-dither
31 - mediatek,mt8192-disp-dither
32 - mediatek,mt8195-disp-dither
33 - mediatek,mt8365-disp-dither
34 - const: mediatek,mt8183-disp-dither
35
36 reg:
37 maxItems: 1
38
39 interrupts:
40 maxItems: 1
41
42 power-domains:
43 description: A phandle and PM domain specifier as defined by bindings of
44 the power controller specified by phandle. See
45 Documentation/devicetree/bindings/power/power-domain.yaml for details.
46
47 clocks:
48 items:
49 - description: DITHER Clock
50
51 mediatek,gce-client-reg:
52 description: The register of client driver can be configured by gce with
53 4 arguments defined in this property, such as phandle of gce, subsys id,
54 register offset and size. Each GCE subsys id is mapping to a client
55 defined in the header include/dt-bindings/gce/<chip>-gce.h.
56 $ref: /schemas/types.yaml#/definitions/phandle-array
57 maxItems: 1
58
59 required:
60 - compatible
61 - reg
62 - interrupts
63 - power-domains
64 - clocks
65
66 additionalProperties: false
67
68 examples:
69 - |
70 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 #include <dt-bindings/clock/mt8183-clk.h>
72 #include <dt-bindings/power/mt8183-power.h>
73 #include <dt-bindings/gce/mt8183-gce.h>
74
75 soc {
76 #address-cells = <2>;
77 #size-cells = <2>;
78
79 dither0: dither@14012000 {
80 compatible = "mediatek,mt8183-disp-dither";
81 reg = <0 0x14012000 0 0x1000>;
82 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
83 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
84 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
85 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
86 };
87 };
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