1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Mediatek display split
8
9 maintainers:
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12
13 description: |
14 Mediatek display split, namely SPLIT, is used to split stream to two
15 encoders.
16 SPLIT device node must be siblings to the central MMSYS_CONFIG node.
17 For a description of the MMSYS_CONFIG binding, see
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19 for details.
20
21 properties:
22 compatible:
23 oneOf:
24 - enum:
25 - mediatek,mt8173-disp-split
26 - mediatek,mt8195-mdp3-split
27 - items:
28 - const: mediatek,mt6795-disp-split
29 - const: mediatek,mt8173-disp-split
30
31 reg:
32 maxItems: 1
33
34 interrupts:
35 maxItems: 1
36
37 power-domains:
38 description: A phandle and PM domain specifier as defined by bindings of
39 the power controller specified by phandle. See
40 Documentation/devicetree/bindings/power/power-domain.yaml for details.
41 maxItems: 1
42
43 mediatek,gce-client-reg:
44 description:
45 The register of display function block to be set by gce. There are 4 arguments,
46 such as gce node, subsys id, offset and register size. The subsys id that is
47 mapping to the register of display function blocks is defined in the gce header
48 include/dt-bindings/gce/<chip>-gce.h of each chips.
49 $ref: /schemas/types.yaml#/definitions/phandle-array
50 items:
51 items:
52 - description: phandle of GCE
53 - description: GCE subsys id
54 - description: register offset
55 - description: register size
56 maxItems: 1
57
58 clocks:
59 items:
60 - description: SPLIT Clock
61 - description: Used for interfacing with the HDMI RX signal source.
62 - description: Paired with receiving HDMI RX metadata.
63 minItems: 1
64
65 required:
66 - compatible
67 - reg
68 - power-domains
69 - clocks
70
71 allOf:
72 - if:
73 properties:
74 compatible:
75 contains:
76 const: mediatek,mt8195-mdp3-split
77
78 then:
79 properties:
80 clocks:
81 minItems: 3
82
83 required:
84 - mediatek,gce-client-reg
85
86 - if:
87 properties:
88 compatible:
89 contains:
90 const: mediatek,mt8173-disp-split
91
92 then:
93 properties:
94 clocks:
95 maxItems: 1
96
97 additionalProperties: false
98
99 examples:
100 - |
101 #include <dt-bindings/clock/mt8173-clk.h>
102 #include <dt-bindings/power/mt8173-power.h>
103
104 soc {
105 #address-cells = <2>;
106 #size-cells = <2>;
107
108 split0: split@14018000 {
109 compatible = "mediatek,mt8173-disp-split";
110 reg = <0 0x14018000 0 0x1000>;
111 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
112 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
113 };
114 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.