1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 %YAML 1.2 3 --- 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 7 title: Mediatek Write Direct Memory Access 8 9 maintainers: 10 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11 - Philipp Zabel <p.zabel@pengutronix.de> 12 13 description: | 14 Mediatek Write Direct Memory Access(WDMA) component used to write 15 the data into DMA. 16 WDMA device node must be siblings to the central MMSYS_CONFIG node. 17 For a description of the MMSYS_CONFIG binding, see 18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 19 for details. 20 21 properties: 22 compatible: 23 oneOf: 24 - enum: 25 - mediatek,mt8173-disp-wdma 26 - items: 27 - const: mediatek,mt6795-disp-wdma 28 - const: mediatek,mt8173-disp-wdma 29 30 reg: 31 maxItems: 1 32 33 interrupts: 34 maxItems: 1 35 36 power-domains: 37 description: A phandle and PM domain specifier as defined by bindings of 38 the power controller specified by phandle. See 39 Documentation/devicetree/bindings/power/power-domain.yaml for details. 40 41 clocks: 42 items: 43 - description: WDMA Clock 44 45 iommus: 46 description: 47 This property should point to the respective IOMMU block with master port as argument, 48 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. 49 50 mediatek,gce-client-reg: 51 description: The register of client driver can be configured by gce with 52 4 arguments defined in this property, such as phandle of gce, subsys id, 53 register offset and size. Each GCE subsys id is mapping to a client 54 defined in the header include/dt-bindings/gce/<chip>-gce.h. 55 $ref: /schemas/types.yaml#/definitions/phandle-array 56 maxItems: 1 57 58 required: 59 - compatible 60 - reg 61 - interrupts 62 - power-domains 63 - clocks 64 - iommus 65 66 additionalProperties: false 67 68 examples: 69 - | 70 #include <dt-bindings/interrupt-controller/arm-gic.h> 71 #include <dt-bindings/clock/mt8173-clk.h> 72 #include <dt-bindings/power/mt8173-power.h> 73 #include <dt-bindings/gce/mt8173-gce.h> 74 #include <dt-bindings/memory/mt8173-larb-port.h> 75 76 soc { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 80 wdma0: wdma@14011000 { 81 compatible = "mediatek,mt8173-disp-wdma"; 82 reg = <0 0x14011000 0 0x1000>; 83 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 84 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 85 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 86 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 87 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 88 }; 89 };
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