1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MSM Display Port Controller
8
9 maintainers:
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12 description: |
13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort interface specification.
15
16 properties:
17 compatible:
18 oneOf:
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp
24 - qcom,sc8180x-edp
25 - qcom,sc8280xp-dp
26 - qcom,sc8280xp-edp
27 - qcom,sdm845-dp
28 - qcom,sm8350-dp
29 - qcom,sm8650-dp
30 - items:
31 - enum:
32 - qcom,sm6350-dp
33 - qcom,sm8150-dp
34 - qcom,sm8250-dp
35 - qcom,sm8450-dp
36 - qcom,sm8550-dp
37 - const: qcom,sm8350-dp
38
39 reg:
40 minItems: 4
41 items:
42 - description: ahb register block
43 - description: aux register block
44 - description: link register block
45 - description: p0 register block
46 - description: p1 register block
47
48 interrupts:
49 maxItems: 1
50
51 clocks:
52 items:
53 - description: AHB clock to enable register access
54 - description: Display Port AUX clock
55 - description: Display Port Link clock
56 - description: Link interface clock between DP and PHY
57 - description: Display Port Pixel clock
58
59 clock-names:
60 items:
61 - const: core_iface
62 - const: core_aux
63 - const: ctrl_link
64 - const: ctrl_link_iface
65 - const: stream_pixel
66
67 assigned-clocks:
68 items:
69 - description: link clock source
70 - description: pixel clock source
71
72 assigned-clock-parents:
73 items:
74 - description: phy 0 parent
75 - description: phy 1 parent
76
77 phys:
78 maxItems: 1
79
80 phy-names:
81 items:
82 - const: dp
83
84 operating-points-v2: true
85
86 opp-table:
87 type: object
88
89 power-domains:
90 maxItems: 1
91
92 aux-bus:
93 $ref: /schemas/display/dp-aux-bus.yaml#
94
95 data-lanes:
96 $ref: /schemas/types.yaml#/definitions/uint32-array
97 deprecated: true
98 minItems: 1
99 maxItems: 4
100 items:
101 maximum: 3
102
103 "#sound-dai-cells":
104 const: 0
105
106 vdda-0p9-supply:
107 deprecated: true
108 vdda-1p2-supply:
109 deprecated: true
110
111 ports:
112 $ref: /schemas/graph.yaml#/properties/ports
113 properties:
114 port@0:
115 $ref: /schemas/graph.yaml#/properties/port
116 description: Input endpoint of the controller
117
118 port@1:
119 $ref: /schemas/graph.yaml#/$defs/port-base
120 unevaluatedProperties: false
121 description: Output endpoint of the controller
122 properties:
123 endpoint:
124 $ref: /schemas/media/video-interfaces.yaml#
125 unevaluatedProperties: false
126 properties:
127 data-lanes:
128 minItems: 1
129 maxItems: 4
130 items:
131 enum: [ 0, 1, 2, 3 ]
132
133 link-frequencies:
134 minItems: 1
135 maxItems: 4
136 items:
137 enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
138
139 required:
140 - port@0
141 - port@1
142
143 required:
144 - compatible
145 - reg
146 - interrupts
147 - clocks
148 - clock-names
149 - phys
150 - phy-names
151 - power-domains
152 - ports
153
154 allOf:
155 # AUX BUS does not exist on DP controllers
156 # Audio output also is present only on DP output
157 # p1 regions is present on DP, but not on eDP
158 - if:
159 properties:
160 compatible:
161 contains:
162 enum:
163 - qcom,sc7280-edp
164 - qcom,sc8180x-edp
165 - qcom,sc8280xp-edp
166 then:
167 properties:
168 "#sound-dai-cells": false
169 else:
170 properties:
171 aux-bus: false
172 reg:
173 minItems: 5
174 required:
175 - "#sound-dai-cells"
176
177 additionalProperties: false
178
179 examples:
180 - |
181 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
183 #include <dt-bindings/power/qcom-rpmpd.h>
184
185 displayport-controller@ae90000 {
186 compatible = "qcom,sc7180-dp";
187 reg = <0xae90000 0x200>,
188 <0xae90200 0x200>,
189 <0xae90400 0xc00>,
190 <0xae91000 0x400>,
191 <0xae91400 0x400>;
192 interrupt-parent = <&mdss>;
193 interrupts = <12>;
194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
198 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
199 clock-names = "core_iface", "core_aux",
200 "ctrl_link",
201 "ctrl_link_iface", "stream_pixel";
202
203 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
204 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
205
206 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
207
208 phys = <&dp_phy>;
209 phy-names = "dp";
210
211 #sound-dai-cells = <0>;
212
213 power-domains = <&rpmhpd SC7180_CX>;
214
215 ports {
216 #address-cells = <1>;
217 #size-cells = <0>;
218
219 port@0 {
220 reg = <0>;
221 endpoint {
222 remote-endpoint = <&dpu_intf0_out>;
223 };
224 };
225
226 port@1 {
227 reg = <1>;
228 endpoint {
229 remote-endpoint = <&typec>;
230 data-lanes = <0 1>;
231 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
232 };
233 };
234 };
235 };
236 ...
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