1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Display DSI 10nm PHY
8
9 maintainers:
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12 allOf:
13 - $ref: dsi-phy-common.yaml#
14
15 properties:
16 compatible:
17 enum:
18 - qcom,dsi-phy-10nm
19 - qcom,dsi-phy-10nm-8998
20
21 reg:
22 items:
23 - description: dsi phy register set
24 - description: dsi phy lane register set
25 - description: dsi pll register set
26
27 reg-names:
28 items:
29 - const: dsi_phy
30 - const: dsi_phy_lane
31 - const: dsi_pll
32
33 vdds-supply:
34 description: |
35 Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
36 connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
37
38 qcom,phy-rescode-offset-top:
39 $ref: /schemas/types.yaml#/definitions/int8-array
40 maxItems: 5
41 description:
42 Integer array of offset for pull-up legs rescode for all five lanes.
43 To offset the drive strength from the calibrated value in an increasing
44 manner, -32 is the weakest and +31 is the strongest.
45 items:
46 minimum: -32
47 maximum: 31
48
49 qcom,phy-rescode-offset-bot:
50 $ref: /schemas/types.yaml#/definitions/int8-array
51 maxItems: 5
52 description:
53 Integer array of offset for pull-down legs rescode for all five lanes.
54 To offset the drive strength from the calibrated value in a decreasing
55 manner, -32 is the weakest and +31 is the strongest.
56 items:
57 minimum: -32
58 maximum: 31
59
60 qcom,phy-drive-ldo-level:
61 $ref: /schemas/types.yaml#/definitions/uint32
62 description:
63 The PHY LDO has an amplitude tuning feature to adjust the LDO output
64 for the HSTX drive. Use supported levels (mV) to offset the drive level
65 from the default value.
66 enum: [ 375, 400, 425, 450, 475, 500 ]
67
68 required:
69 - compatible
70 - reg
71 - reg-names
72
73 unevaluatedProperties: false
74
75 examples:
76 - |
77 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
78 #include <dt-bindings/clock/qcom,rpmh.h>
79
80 dsi-phy@ae94400 {
81 compatible = "qcom,dsi-phy-10nm";
82 reg = <0x0ae94400 0x200>,
83 <0x0ae94600 0x280>,
84 <0x0ae94a00 0x1e0>;
85 reg-names = "dsi_phy",
86 "dsi_phy_lane",
87 "dsi_pll";
88
89 #clock-cells = <1>;
90 #phy-cells = <0>;
91
92 vdds-supply = <&vdda_mipi_dsi0_pll>;
93 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
94 <&rpmhcc RPMH_CXO_CLK>;
95 clock-names = "iface", "ref";
96
97 qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
98 qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
99 qcom,phy-drive-ldo-level = <400>;
100 };
101 ...
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