1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Display DSI 28nm PHY
8
9 maintainers:
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12 allOf:
13 - $ref: dsi-phy-common.yaml#
14
15 properties:
16 compatible:
17 enum:
18 - qcom,dsi-phy-28nm-8226
19 - qcom,dsi-phy-28nm-8937
20 - qcom,dsi-phy-28nm-8960
21 - qcom,dsi-phy-28nm-hpm
22 - qcom,dsi-phy-28nm-hpm-fam-b
23 - qcom,dsi-phy-28nm-lp
24
25 reg:
26 items:
27 - description: dsi pll register set
28 - description: dsi phy register set
29 - description: dsi phy regulator register set
30
31 reg-names:
32 items:
33 - const: dsi_pll
34 - const: dsi_phy
35 - const: dsi_phy_regulator
36
37 vddio-supply:
38 description: Phandle to vdd-io regulator device node.
39
40 qcom,dsi-phy-regulator-ldo-mode:
41 type: boolean
42 description: Indicates if the LDO mode PHY regulator is wanted.
43
44 required:
45 - compatible
46 - reg
47 - reg-names
48 - vddio-supply
49
50 unevaluatedProperties: false
51
52 examples:
53 - |
54 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
55 #include <dt-bindings/clock/qcom,rpmh.h>
56
57 dsi-phy@fd922a00 {
58 compatible = "qcom,dsi-phy-28nm-lp";
59 reg = <0xfd922a00 0xd4>,
60 <0xfd922b00 0x2b0>,
61 <0xfd922d80 0x7b>;
62 reg-names = "dsi_pll",
63 "dsi_phy",
64 "dsi_phy_regulator";
65
66 #clock-cells = <1>;
67 #phy-cells = <0>;
68
69 vddio-supply = <&vddio_reg>;
70
71 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
72 <&rpmhcc RPMH_CXO_CLK>;
73 clock-names = "iface", "ref";
74 };
75 ...
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