1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm QCM220 Display MDSS
8
9 maintainers:
10 - Loic Poulain <loic.poulain@linaro.org>
11
12 description:
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15 are mentioned for QCM2290 target.
16
17 $ref: /schemas/display/msm/mdss-common.yaml#
18
19 properties:
20 compatible:
21 const: qcom,qcm2290-mdss
22
23 clocks:
24 items:
25 - description: Display AHB clock from gcc
26 - description: Display AXI clock
27 - description: Display core clock
28
29 clock-names:
30 items:
31 - const: iface
32 - const: bus
33 - const: core
34
35 iommus:
36 maxItems: 2
37
38 interconnects:
39 items:
40 - description: Interconnect path from mdp0 port to the data bus
41 - description: Interconnect path from CPU to the reg bus
42
43 interconnect-names:
44 items:
45 - const: mdp0-mem
46 - const: cpu-cfg
47
48 patternProperties:
49 "^display-controller@[0-9a-f]+$":
50 type: object
51 additionalProperties: true
52
53 properties:
54 compatible:
55 const: qcom,qcm2290-dpu
56
57 "^dsi@[0-9a-f]+$":
58 type: object
59 additionalProperties: true
60
61 properties:
62 compatible:
63 items:
64 - const: qcom,qcm2290-dsi-ctrl
65 - const: qcom,mdss-dsi-ctrl
66
67 "^phy@[0-9a-f]+$":
68 type: object
69 additionalProperties: true
70
71 properties:
72 compatible:
73 const: qcom,dsi-phy-14nm-2290
74
75 required:
76 - compatible
77
78 unevaluatedProperties: false
79
80 examples:
81 - |
82 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
83 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
84 #include <dt-bindings/clock/qcom,rpmcc.h>
85 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 #include <dt-bindings/interconnect/qcom,qcm2290.h>
87 #include <dt-bindings/power/qcom-rpmpd.h>
88
89 display-subsystem@5e00000 {
90 #address-cells = <1>;
91 #size-cells = <1>;
92 compatible = "qcom,qcm2290-mdss";
93 reg = <0x05e00000 0x1000>;
94 reg-names = "mdss";
95 power-domains = <&dispcc MDSS_GDSC>;
96 clocks = <&gcc GCC_DISP_AHB_CLK>,
97 <&gcc GCC_DISP_HF_AXI_CLK>,
98 <&dispcc DISP_CC_MDSS_MDP_CLK>;
99 clock-names = "iface", "bus", "core";
100
101 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-controller;
103 #interrupt-cells = <1>;
104
105 interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>,
106 <&bimc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
107 interconnect-names = "mdp0-mem",
108 "cpu-cfg";
109
110 iommus = <&apps_smmu 0x420 0x2>,
111 <&apps_smmu 0x421 0x0>;
112 ranges;
113
114 display-controller@5e01000 {
115 compatible = "qcom,qcm2290-dpu";
116 reg = <0x05e01000 0x8f000>,
117 <0x05eb0000 0x2008>;
118 reg-names = "mdp", "vbif";
119
120 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_MDP_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
124 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
125 clock-names = "bus", "iface", "core", "lut", "vsync";
126
127 operating-points-v2 = <&mdp_opp_table>;
128 power-domains = <&rpmpd QCM2290_VDDCX>;
129
130 interrupt-parent = <&mdss>;
131 interrupts = <0>;
132
133 ports {
134 #address-cells = <1>;
135 #size-cells = <0>;
136
137 port@0 {
138 reg = <0>;
139 dpu_intf1_out: endpoint {
140 remote-endpoint = <&dsi0_in>;
141 };
142 };
143 };
144 };
145
146 dsi@5e94000 {
147 compatible = "qcom,qcm2290-dsi-ctrl",
148 "qcom,mdss-dsi-ctrl";
149 reg = <0x05e94000 0x400>;
150 reg-names = "dsi_ctrl";
151
152 interrupt-parent = <&mdss>;
153 interrupts = <4>;
154
155 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
156 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
157 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
158 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
159 <&dispcc DISP_CC_MDSS_AHB_CLK>,
160 <&gcc GCC_DISP_HF_AXI_CLK>;
161 clock-names = "byte",
162 "byte_intf",
163 "pixel",
164 "core",
165 "iface",
166 "bus";
167 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
168 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
169
170 operating-points-v2 = <&dsi_opp_table>;
171 power-domains = <&rpmpd QCM2290_VDDCX>;
172
173 phys = <&dsi0_phy>;
174 phy-names = "dsi";
175
176 #address-cells = <1>;
177 #size-cells = <0>;
178
179 ports {
180 #address-cells = <1>;
181 #size-cells = <0>;
182
183 port@0 {
184 reg = <0>;
185 dsi0_in: endpoint {
186 remote-endpoint = <&dpu_intf1_out>;
187 };
188 };
189
190 port@1 {
191 reg = <1>;
192 dsi0_out: endpoint {
193 };
194 };
195 };
196 };
197
198 dsi0_phy: phy@5e94400 {
199 compatible = "qcom,dsi-phy-14nm-2290";
200 reg = <0x05e94400 0x100>,
201 <0x05e94500 0x300>,
202 <0x05e94800 0x188>;
203 reg-names = "dsi_phy",
204 "dsi_phy_lane",
205 "dsi_pll";
206
207 #clock-cells = <1>;
208 #phy-cells = <0>;
209
210 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
211 clock-names = "iface", "ref";
212 vcca-supply = <&vreg_dsi_phy>;
213 };
214 };
215 ...
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