1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SC7180 Display MDSS
8
9 maintainers:
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12 description:
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SC7180 target.
16
17 $ref: /schemas/display/msm/mdss-common.yaml#
18
19 properties:
20 compatible:
21 const: qcom,sc7180-mdss
22
23 clocks:
24 items:
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
27 - description: Display core clock
28
29 clock-names:
30 items:
31 - const: iface
32 - const: ahb
33 - const: core
34
35 iommus:
36 maxItems: 1
37
38 interconnects:
39 items:
40 - description: Interconnect path from mdp0 port to the data bus
41 - description: Interconnect path from CPU to the reg bus
42
43 interconnect-names:
44 items:
45 - const: mdp0-mem
46 - const: cpu-cfg
47
48 patternProperties:
49 "^display-controller@[0-9a-f]+$":
50 type: object
51 additionalProperties: true
52
53 properties:
54 compatible:
55 const: qcom,sc7180-dpu
56
57 "^displayport-controller@[0-9a-f]+$":
58 type: object
59 additionalProperties: true
60
61 properties:
62 compatible:
63 const: qcom,sc7180-dp
64
65 "^dsi@[0-9a-f]+$":
66 type: object
67 additionalProperties: true
68
69 properties:
70 compatible:
71 items:
72 - const: qcom,sc7180-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
74
75 "^phy@[0-9a-f]+$":
76 type: object
77 additionalProperties: true
78
79 properties:
80 compatible:
81 const: qcom,dsi-phy-10nm
82
83 required:
84 - compatible
85
86 unevaluatedProperties: false
87
88 examples:
89 - |
90 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
91 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
92 #include <dt-bindings/clock/qcom,rpmh.h>
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #include <dt-bindings/interconnect/qcom,sdm845.h>
95 #include <dt-bindings/power/qcom-rpmpd.h>
96
97 display-subsystem@ae00000 {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 compatible = "qcom,sc7180-mdss";
101 reg = <0xae00000 0x1000>;
102 reg-names = "mdss";
103 power-domains = <&dispcc MDSS_GDSC>;
104 clocks = <&gcc GCC_DISP_AHB_CLK>,
105 <&dispcc DISP_CC_MDSS_AHB_CLK>,
106 <&dispcc DISP_CC_MDSS_MDP_CLK>;
107 clock-names = "iface", "ahb", "core";
108
109 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-controller;
111 #interrupt-cells = <1>;
112
113 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
114 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
115 interconnect-names = "mdp0-mem",
116 "cpu-cfg";
117
118 iommus = <&apps_smmu 0x800 0x2>;
119 ranges;
120
121 display-controller@ae01000 {
122 compatible = "qcom,sc7180-dpu";
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
125
126 reg-names = "mdp", "vbif";
127
128 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_ROT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134 clock-names = "bus", "iface", "rot", "lut", "core",
135 "vsync";
136
137 interrupt-parent = <&mdss>;
138 interrupts = <0>;
139 power-domains = <&rpmhpd SC7180_CX>;
140 operating-points-v2 = <&mdp_opp_table>;
141
142 ports {
143 #address-cells = <1>;
144 #size-cells = <0>;
145
146 port@0 {
147 reg = <0>;
148 dpu_intf1_out: endpoint {
149 remote-endpoint = <&dsi0_in>;
150 };
151 };
152
153 port@2 {
154 reg = <2>;
155 dpu_intf0_out: endpoint {
156 remote-endpoint = <&dp_in>;
157 };
158 };
159 };
160 };
161
162 dsi@ae94000 {
163 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
164 reg = <0x0ae94000 0x400>;
165 reg-names = "dsi_ctrl";
166
167 interrupt-parent = <&mdss>;
168 interrupts = <4>;
169
170 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
171 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
172 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
173 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
174 <&dispcc DISP_CC_MDSS_AHB_CLK>,
175 <&gcc GCC_DISP_HF_AXI_CLK>;
176 clock-names = "byte",
177 "byte_intf",
178 "pixel",
179 "core",
180 "iface",
181 "bus";
182
183 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
184 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
185
186 operating-points-v2 = <&dsi_opp_table>;
187 power-domains = <&rpmhpd SC7180_CX>;
188
189 phys = <&dsi_phy>;
190 phy-names = "dsi";
191
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 ports {
196 #address-cells = <1>;
197 #size-cells = <0>;
198
199 port@0 {
200 reg = <0>;
201 dsi0_in: endpoint {
202 remote-endpoint = <&dpu_intf1_out>;
203 };
204 };
205
206 port@1 {
207 reg = <1>;
208 dsi0_out: endpoint {
209 };
210 };
211 };
212
213 dsi_opp_table: opp-table {
214 compatible = "operating-points-v2";
215
216 opp-187500000 {
217 opp-hz = /bits/ 64 <187500000>;
218 required-opps = <&rpmhpd_opp_low_svs>;
219 };
220
221 opp-300000000 {
222 opp-hz = /bits/ 64 <300000000>;
223 required-opps = <&rpmhpd_opp_svs>;
224 };
225
226 opp-358000000 {
227 opp-hz = /bits/ 64 <358000000>;
228 required-opps = <&rpmhpd_opp_svs_l1>;
229 };
230 };
231 };
232
233 dsi_phy: phy@ae94400 {
234 compatible = "qcom,dsi-phy-10nm";
235 reg = <0x0ae94400 0x200>,
236 <0x0ae94600 0x280>,
237 <0x0ae94a00 0x1e0>;
238 reg-names = "dsi_phy",
239 "dsi_phy_lane",
240 "dsi_pll";
241
242 #clock-cells = <1>;
243 #phy-cells = <0>;
244
245 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
246 <&rpmhcc RPMH_CXO_CLK>;
247 clock-names = "iface", "ref";
248 vdds-supply = <&vreg_dsi_phy>;
249 };
250
251 displayport-controller@ae90000 {
252 compatible = "qcom,sc7180-dp";
253
254 reg = <0xae90000 0x200>,
255 <0xae90200 0x200>,
256 <0xae90400 0xc00>,
257 <0xae91000 0x400>,
258 <0xae91400 0x400>;
259
260 interrupt-parent = <&mdss>;
261 interrupts = <12>;
262
263 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
264 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
265 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
266 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
267 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
268 clock-names = "core_iface", "core_aux", "ctrl_link",
269 "ctrl_link_iface", "stream_pixel";
270 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
271 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
272 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
273 phys = <&dp_phy>;
274 phy-names = "dp";
275
276 operating-points-v2 = <&dp_opp_table>;
277 power-domains = <&rpmhpd SC7180_CX>;
278
279 #sound-dai-cells = <0>;
280
281 ports {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 port@0 {
285 reg = <0>;
286 dp_in: endpoint {
287 remote-endpoint = <&dpu_intf0_out>;
288 };
289 };
290
291 port@1 {
292 reg = <1>;
293 dp_out: endpoint { };
294 };
295 };
296
297 dp_opp_table: opp-table {
298 compatible = "operating-points-v2";
299
300 opp-160000000 {
301 opp-hz = /bits/ 64 <160000000>;
302 required-opps = <&rpmhpd_opp_low_svs>;
303 };
304
305 opp-270000000 {
306 opp-hz = /bits/ 64 <270000000>;
307 required-opps = <&rpmhpd_opp_svs>;
308 };
309
310 opp-540000000 {
311 opp-hz = /bits/ 64 <540000000>;
312 required-opps = <&rpmhpd_opp_svs_l1>;
313 };
314
315 opp-810000000 {
316 opp-hz = /bits/ 64 <810000000>;
317 required-opps = <&rpmhpd_opp_nom>;
318 };
319 };
320 };
321 };
322 ...
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.