1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SM7150 Display Processing Unit (DPU)
8
9 maintainers:
10 - Danila Tikhonov <danila@jiaxyga.com>
11
12 $ref: /schemas/display/msm/dpu-common.yaml#
13
14 properties:
15 compatible:
16 const: qcom,sm7150-dpu
17
18 reg:
19 items:
20 - description: Address offset and size for mdp register set
21 - description: Address offset and size for vbif register set
22
23 reg-names:
24 items:
25 - const: mdp
26 - const: vbif
27
28 clocks:
29 items:
30 - description: Display hf axi clock
31 - description: Display ahb clock
32 - description: Display rotator clock
33 - description: Display lut clock
34 - description: Display core clock
35 - description: Display vsync clock
36
37 clock-names:
38 items:
39 - const: bus
40 - const: iface
41 - const: rot
42 - const: lut
43 - const: core
44 - const: vsync
45
46 required:
47 - compatible
48 - reg
49 - reg-names
50 - clocks
51 - clock-names
52
53 unevaluatedProperties: false
54
55 examples:
56 - |
57 #include <dt-bindings/interrupt-controller/arm-gic.h>
58 #include <dt-bindings/power/qcom,rpmhpd.h>
59
60 display-controller@ae01000 {
61 compatible = "qcom,sm7150-dpu";
62 reg = <0x0ae01000 0x8f000>,
63 <0x0aeb0000 0x2008>;
64 reg-names = "mdp", "vbif";
65
66 clocks = <&gcc_disp_hf_axi_clk>,
67 <&dispcc_mdss_ahb_clk>,
68 <&dispcc_mdss_rot_clk>,
69 <&dispcc_mdss_mdp_lut_clk>,
70 <&dispcc_mdss_mdp_clk>,
71 <&dispcc_mdss_vsync_clk>;
72 clock-names = "bus",
73 "iface",
74 "rot",
75 "lut",
76 "core",
77 "vsync";
78
79 assigned-clocks = <&dispcc_mdss_vsync_clk>;
80 assigned-clock-rates = <19200000>;
81
82 operating-points-v2 = <&mdp_opp_table>;
83 power-domains = <&rpmhpd RPMHPD_CX>;
84
85 interrupt-parent = <&mdss>;
86 interrupts = <0>;
87
88 ports {
89 #address-cells = <1>;
90 #size-cells = <0>;
91
92 port@0 {
93 reg = <0>;
94 dpu_intf1_out: endpoint {
95 remote-endpoint = <&mdss_dsi0_in>;
96 };
97 };
98
99 port@1 {
100 reg = <1>;
101 dpu_intf2_out: endpoint {
102 remote-endpoint = <&mdss_dsi1_in>;
103 };
104 };
105
106 port@2 {
107 reg = <2>;
108 dpu_intf0_out: endpoint {
109 remote-endpoint = <&dp_in>;
110 };
111 };
112 };
113
114 mdp_opp_table: opp-table {
115 compatible = "operating-points-v2";
116
117 opp-19200000 {
118 opp-hz = /bits/ 64 <19200000>;
119 required-opps = <&rpmhpd_opp_min_svs>;
120 };
121
122 opp-200000000 {
123 opp-hz = /bits/ 64 <200000000>;
124 required-opps = <&rpmhpd_opp_low_svs>;
125 };
126
127 opp-300000000 {
128 opp-hz = /bits/ 64 <300000000>;
129 required-opps = <&rpmhpd_opp_svs>;
130 };
131
132 opp-344000000 {
133 opp-hz = /bits/ 64 <344000000>;
134 required-opps = <&rpmhpd_opp_svs_l1>;
135 };
136
137 opp-430000000 {
138 opp-hz = /bits/ 64 <430000000>;
139 required-opps = <&rpmhpd_opp_nom>;
140 };
141 };
142 };
143 ...
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