1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SM7150 Display MDSS
8
9 maintainers:
10 - Danila Tikhonov <danila@jiaxyga.com>
11
12 description:
13 SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
15
16 $ref: /schemas/display/msm/mdss-common.yaml#
17
18 properties:
19 compatible:
20 const: qcom,sm7150-mdss
21
22 clocks:
23 items:
24 - description: Display ahb clock from gcc
25 - description: Display hf axi clock
26 - description: Display sf axi clock
27 - description: Display core clock
28
29 clock-names:
30 items:
31 - const: iface
32 - const: bus
33 - const: nrt_bus
34 - const: core
35
36 iommus:
37 maxItems: 1
38
39 interconnects:
40 items:
41 - description: Interconnect path from mdp0 port to the data bus
42 - description: Interconnect path from mdp1 port to the data bus
43 - description: Interconnect path from CPU to the reg bus
44
45 interconnect-names:
46 items:
47 - const: mdp0-mem
48 - const: mdp1-mem
49 - const: cpu-cfg
50
51 patternProperties:
52 "^display-controller@[0-9a-f]+$":
53 type: object
54 additionalProperties: true
55 properties:
56 compatible:
57 const: qcom,sm7150-dpu
58
59 "^displayport-controller@[0-9a-f]+$":
60 type: object
61 additionalProperties: true
62 properties:
63 compatible:
64 const: qcom,sm7150-dp
65
66 "^dsi@[0-9a-f]+$":
67 type: object
68 additionalProperties: true
69 properties:
70 compatible:
71 items:
72 - const: qcom,sm7150-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
74
75 "^phy@[0-9a-f]+$":
76 type: object
77 additionalProperties: true
78 properties:
79 compatible:
80 const: qcom,dsi-phy-10nm
81
82 required:
83 - compatible
84
85 unevaluatedProperties: false
86
87 examples:
88 - |
89 #include <dt-bindings/clock/qcom,rpmh.h>
90 #include <dt-bindings/interconnect/qcom,icc.h>
91 #include <dt-bindings/interconnect/qcom,sm7150-rpmh.h>
92 #include <dt-bindings/interrupt-controller/arm-gic.h>
93 #include <dt-bindings/power/qcom,rpmhpd.h>
94
95 display-subsystem@ae00000 {
96 compatible = "qcom,sm7150-mdss";
97 reg = <0x0ae00000 0x1000>;
98 reg-names = "mdss";
99
100 power-domains = <&dispcc_mdss_gdsc>;
101
102 clocks = <&dispcc_mdss_ahb_clk>,
103 <&gcc_disp_hf_axi_clk>,
104 <&gcc_disp_sf_axi_clk>,
105 <&dispcc_mdss_mdp_clk>;
106 clock-names = "iface",
107 "bus",
108 "nrt_bus",
109 "core";
110
111 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-controller;
113 #interrupt-cells = <1>;
114
115 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
116 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
117 <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS
118 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
119 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
120 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
121 interconnect-names = "mdp0-mem",
122 "mdp1-mem",
123 "cpu-cfg";
124
125 iommus = <&apps_smmu 0x800 0x440>;
126
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges;
130
131 display-controller@ae01000 {
132 compatible = "qcom,sm7150-dpu";
133 reg = <0x0ae01000 0x8f000>,
134 <0x0aeb0000 0x2008>;
135 reg-names = "mdp", "vbif";
136
137 clocks = <&gcc_disp_hf_axi_clk>,
138 <&dispcc_mdss_ahb_clk>,
139 <&dispcc_mdss_rot_clk>,
140 <&dispcc_mdss_mdp_lut_clk>,
141 <&dispcc_mdss_mdp_clk>,
142 <&dispcc_mdss_vsync_clk>;
143 clock-names = "bus",
144 "iface",
145 "rot",
146 "lut",
147 "core",
148 "vsync";
149
150 assigned-clocks = <&dispcc_mdss_vsync_clk>;
151 assigned-clock-rates = <19200000>;
152
153 operating-points-v2 = <&mdp_opp_table>;
154 power-domains = <&rpmhpd RPMHPD_CX>;
155
156 interrupt-parent = <&mdss>;
157 interrupts = <0>;
158
159 ports {
160 #address-cells = <1>;
161 #size-cells = <0>;
162
163 port@0 {
164 reg = <0>;
165 dpu_intf1_out: endpoint {
166 remote-endpoint = <&mdss_dsi0_in>;
167 };
168 };
169
170 port@1 {
171 reg = <1>;
172 dpu_intf2_out: endpoint {
173 remote-endpoint = <&mdss_dsi1_in>;
174 };
175 };
176
177 port@2 {
178 reg = <2>;
179 dpu_intf0_out: endpoint {
180 remote-endpoint = <&dp_in>;
181 };
182 };
183 };
184
185 mdp_opp_table: opp-table {
186 compatible = "operating-points-v2";
187
188 opp-19200000 {
189 opp-hz = /bits/ 64 <19200000>;
190 required-opps = <&rpmhpd_opp_min_svs>;
191 };
192
193 opp-200000000 {
194 opp-hz = /bits/ 64 <200000000>;
195 required-opps = <&rpmhpd_opp_low_svs>;
196 };
197
198 opp-300000000 {
199 opp-hz = /bits/ 64 <300000000>;
200 required-opps = <&rpmhpd_opp_svs>;
201 };
202
203 opp-344000000 {
204 opp-hz = /bits/ 64 <344000000>;
205 required-opps = <&rpmhpd_opp_svs_l1>;
206 };
207
208 opp-430000000 {
209 opp-hz = /bits/ 64 <430000000>;
210 required-opps = <&rpmhpd_opp_nom>;
211 };
212 };
213 };
214
215 dsi@ae94000 {
216 compatible = "qcom,sm7150-dsi-ctrl",
217 "qcom,mdss-dsi-ctrl";
218 reg = <0x0ae94000 0x400>;
219 reg-names = "dsi_ctrl";
220
221 interrupt-parent = <&mdss>;
222 interrupts = <4>;
223
224 clocks = <&dispcc_mdss_byte0_clk>,
225 <&dispcc_mdss_byte0_intf_clk>,
226 <&dispcc_mdss_pclk0_clk>,
227 <&dispcc_mdss_esc0_clk>,
228 <&dispcc_mdss_ahb_clk>,
229 <&gcc_disp_hf_axi_clk>;
230 clock-names = "byte",
231 "byte_intf",
232 "pixel",
233 "core",
234 "iface",
235 "bus";
236
237 assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
238 <&dispcc_mdss_pclk0_clk_src>;
239 assigned-clock-parents = <&mdss_dsi0_phy 0>,
240 <&mdss_dsi0_phy 1>;
241
242 operating-points-v2 = <&dsi_opp_table>;
243 power-domains = <&rpmhpd RPMHPD_CX>;
244
245 phys = <&mdss_dsi0_phy>;
246 phy-names = "dsi";
247
248 #address-cells = <1>;
249 #size-cells = <0>;
250
251 ports {
252 #address-cells = <1>;
253 #size-cells = <0>;
254
255 port@0 {
256 reg = <0>;
257 mdss_dsi0_in: endpoint {
258 remote-endpoint = <&dpu_intf1_out>;
259 };
260 };
261
262 port@1 {
263 reg = <1>;
264 mdss_dsi0_out: endpoint {
265 };
266 };
267 };
268
269 dsi_opp_table: opp-table {
270 compatible = "operating-points-v2";
271
272 opp-180000000 {
273 opp-hz = /bits/ 64 <180000000>;
274 required-opps = <&rpmhpd_opp_low_svs>;
275 };
276
277 opp-275000000 {
278 opp-hz = /bits/ 64 <275000000>;
279 required-opps = <&rpmhpd_opp_svs>;
280 };
281
282 opp-358000000 {
283 opp-hz = /bits/ 64 <358000000>;
284 required-opps = <&rpmhpd_opp_svs_l1>;
285 };
286 };
287 };
288
289 mdss_dsi0_phy: phy@ae94400 {
290 compatible = "qcom,dsi-phy-10nm";
291 reg = <0x0ae94400 0x200>,
292 <0x0ae94600 0x280>,
293 <0x0ae94a00 0x1e0>;
294 reg-names = "dsi_phy",
295 "dsi_phy_lane",
296 "dsi_pll";
297
298 #clock-cells = <1>;
299 #phy-cells = <0>;
300
301 clocks = <&dispcc_mdss_ahb_clk>,
302 <&rpmhcc RPMH_CXO_CLK>;
303 clock-names = "iface", "ref";
304 vdds-supply = <&vdda_mipi_dsi0_pll>;
305 };
306
307 dsi@ae96000 {
308 compatible = "qcom,sm7150-dsi-ctrl",
309 "qcom,mdss-dsi-ctrl";
310 reg = <0x0ae96000 0x400>;
311 reg-names = "dsi_ctrl";
312
313 interrupt-parent = <&mdss>;
314 interrupts = <5>;
315
316 clocks = <&dispcc_mdss_byte1_clk>,
317 <&dispcc_mdss_byte1_intf_clk>,
318 <&dispcc_mdss_pclk1_clk>,
319 <&dispcc_mdss_esc1_clk>,
320 <&dispcc_mdss_ahb_clk>,
321 <&gcc_disp_hf_axi_clk>;
322 clock-names = "byte",
323 "byte_intf",
324 "pixel",
325 "core",
326 "iface",
327 "bus";
328
329 assigned-clocks = <&dispcc_mdss_byte1_clk_src>,
330 <&dispcc_mdss_pclk1_clk_src>;
331 assigned-clock-parents = <&mdss_dsi1_phy 0>,
332 <&mdss_dsi1_phy 1>;
333
334 operating-points-v2 = <&dsi_opp_table>;
335 power-domains = <&rpmhpd RPMHPD_CX>;
336
337 phys = <&mdss_dsi1_phy>;
338 phy-names = "dsi";
339
340 #address-cells = <1>;
341 #size-cells = <0>;
342
343 ports {
344 #address-cells = <1>;
345 #size-cells = <0>;
346
347 port@0 {
348 reg = <0>;
349 mdss_dsi1_in: endpoint {
350 remote-endpoint = <&dpu_intf2_out>;
351 };
352 };
353
354 port@1 {
355 reg = <1>;
356 mdss_dsi1_out: endpoint {
357 };
358 };
359 };
360 };
361
362 mdss_dsi1_phy: phy@ae96400 {
363 compatible = "qcom,dsi-phy-10nm";
364 reg = <0x0ae96400 0x200>,
365 <0x0ae96600 0x280>,
366 <0x0ae96a00 0x1e0>;
367 reg-names = "dsi_phy",
368 "dsi_phy_lane",
369 "dsi_pll";
370
371 #clock-cells = <1>;
372 #phy-cells = <0>;
373
374 clocks = <&dispcc_mdss_ahb_clk>,
375 <&rpmhcc RPMH_CXO_CLK>;
376 clock-names = "iface", "ref";
377 vdds-supply = <&vdda_mipi_dsi1_pll>;
378 };
379
380 displayport-controller@ae90000 {
381 compatible = "qcom,sm7150-dp";
382 reg = <0xae90000 0x200>,
383 <0xae90200 0x200>,
384 <0xae90400 0xc00>,
385 <0xae91000 0x400>,
386 <0xae91400 0x400>;
387
388 interrupt-parent = <&mdss>;
389 interrupts = <12>;
390
391 clocks = <&dispcc_mdss_ahb_clk>,
392 <&dispcc_mdss_dp_aux_clk>,
393 <&dispcc_mdss_dp_link_clk>,
394 <&dispcc_mdss_dp_link_intf_clk>,
395 <&dispcc_mdss_dp_pixel_clk>;
396 clock-names = "core_iface",
397 "core_aux",
398 "ctrl_link",
399 "ctrl_link_iface",
400 "stream_pixel";
401
402 assigned-clocks = <&dispcc_mdss_dp_link_clk_src>,
403 <&dispcc_mdss_dp_pixel_clk_src>;
404 assigned-clock-parents = <&dp_phy 0>,
405 <&dp_phy 1>;
406
407 operating-points-v2 = <&dp_opp_table>;
408 power-domains = <&rpmhpd RPMHPD_CX>;
409
410 phys = <&dp_phy>;
411 phy-names = "dp";
412
413 #sound-dai-cells = <0>;
414
415 ports {
416 #address-cells = <1>;
417 #size-cells = <0>;
418
419 port@0 {
420 reg = <0>;
421 dp_in: endpoint {
422 remote-endpoint = <&dpu_intf0_out>;
423 };
424 };
425
426 port@1 {
427 reg = <1>;
428 dp_out: endpoint {
429 };
430 };
431 };
432
433 dp_opp_table: opp-table {
434 compatible = "operating-points-v2";
435
436 opp-160000000 {
437 opp-hz = /bits/ 64 <160000000>;
438 required-opps = <&rpmhpd_opp_low_svs>;
439 };
440
441 opp-270000000 {
442 opp-hz = /bits/ 64 <270000000>;
443 required-opps = <&rpmhpd_opp_svs>;
444 };
445
446 opp-540000000 {
447 opp-hz = /bits/ 64 <540000000>;
448 required-opps = <&rpmhpd_opp_svs_l1>;
449 };
450
451 opp-810000000 {
452 opp-hz = /bits/ 64 <810000000>;
453 required-opps = <&rpmhpd_opp_nom>;
454 };
455 };
456 };
457 };
458 ...
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