1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 %YAML 1.2 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 7 title: Qualcomm SM8350 Display DPU 8 9 maintainers: 10 - Robert Foss <robert.foss@linaro.org> 11 12 $ref: /schemas/display/msm/dpu-common.yaml# 13 14 properties: 15 compatible: 16 const: qcom,sm8350-dpu 17 18 reg: 19 items: 20 - description: Address offset and size for mdp register set 21 - description: Address offset and size for vbif register set 22 23 reg-names: 24 items: 25 - const: mdp 26 - const: vbif 27 28 clocks: 29 items: 30 - description: Display hf axi clock 31 - description: Display sf axi clock 32 - description: Display ahb clock 33 - description: Display lut clock 34 - description: Display core clock 35 - description: Display vsync clock 36 37 clock-names: 38 items: 39 - const: bus 40 - const: nrt_bus 41 - const: iface 42 - const: lut 43 - const: core 44 - const: vsync 45 46 unevaluatedProperties: false 47 48 examples: 49 - | 50 #include <dt-bindings/clock/qcom,dispcc-sm8350.h> 51 #include <dt-bindings/clock/qcom,gcc-sm8350.h> 52 #include <dt-bindings/interrupt-controller/arm-gic.h> 53 #include <dt-bindings/interconnect/qcom,sm8350.h> 54 #include <dt-bindings/power/qcom,rpmhpd.h> 55 56 display-controller@ae01000 { 57 compatible = "qcom,sm8350-dpu"; 58 reg = <0x0ae01000 0x8f000>, 59 <0x0aeb0000 0x2008>; 60 reg-names = "mdp", "vbif"; 61 62 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 63 <&gcc GCC_DISP_SF_AXI_CLK>, 64 <&dispcc DISP_CC_MDSS_AHB_CLK>, 65 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 66 <&dispcc DISP_CC_MDSS_MDP_CLK>, 67 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 68 clock-names = "bus", 69 "nrt_bus", 70 "iface", 71 "lut", 72 "core", 73 "vsync"; 74 75 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 76 assigned-clock-rates = <19200000>; 77 78 operating-points-v2 = <&mdp_opp_table>; 79 power-domains = <&rpmhpd RPMHPD_MMCX>; 80 81 interrupt-parent = <&mdss>; 82 interrupts = <0>; 83 84 ports { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 port@0 { 89 reg = <0>; 90 dpu_intf1_out: endpoint { 91 remote-endpoint = <&dsi0_in>; 92 }; 93 }; 94 }; 95 96 mdp_opp_table: opp-table { 97 compatible = "operating-points-v2"; 98 99 opp-200000000 { 100 opp-hz = /bits/ 64 <200000000>; 101 required-opps = <&rpmhpd_opp_low_svs>; 102 }; 103 104 opp-300000000 { 105 opp-hz = /bits/ 64 <300000000>; 106 required-opps = <&rpmhpd_opp_svs>; 107 }; 108 109 opp-345000000 { 110 opp-hz = /bits/ 64 <345000000>; 111 required-opps = <&rpmhpd_opp_svs_l1>; 112 }; 113 114 opp-460000000 { 115 opp-hz = /bits/ 64 <460000000>; 116 required-opps = <&rpmhpd_opp_nom>; 117 }; 118 }; 119 }; 120 ...
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