1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm SM8650 Display MDSS
8
9 maintainers:
10 - Neil Armstrong <neil.armstrong@linaro.org>
11
12 description:
13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
15
16 $ref: /schemas/display/msm/mdss-common.yaml#
17
18 properties:
19 compatible:
20 const: qcom,sm8650-mdss
21
22 clocks:
23 items:
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
27
28 iommus:
29 maxItems: 1
30
31 interconnects:
32 maxItems: 2
33
34 interconnect-names:
35 maxItems: 2
36
37 patternProperties:
38 "^display-controller@[0-9a-f]+$":
39 type: object
40 additionalProperties: true
41 properties:
42 compatible:
43 const: qcom,sm8650-dpu
44
45 "^displayport-controller@[0-9a-f]+$":
46 type: object
47 additionalProperties: true
48 properties:
49 compatible:
50 const: qcom,sm8650-dp
51
52 "^dsi@[0-9a-f]+$":
53 type: object
54 additionalProperties: true
55 properties:
56 compatible:
57 items:
58 - const: qcom,sm8650-dsi-ctrl
59 - const: qcom,mdss-dsi-ctrl
60
61 "^phy@[0-9a-f]+$":
62 type: object
63 additionalProperties: true
64 properties:
65 compatible:
66 const: qcom,sm8650-dsi-phy-4nm
67
68 required:
69 - compatible
70
71 unevaluatedProperties: false
72
73 examples:
74 - |
75 #include <dt-bindings/clock/qcom,rpmh.h>
76 #include <dt-bindings/interrupt-controller/arm-gic.h>
77 #include <dt-bindings/power/qcom,rpmhpd.h>
78
79 display-subsystem@ae00000 {
80 compatible = "qcom,sm8650-mdss";
81 reg = <0x0ae00000 0x1000>;
82 reg-names = "mdss";
83
84 resets = <&dispcc_core_bcr>;
85
86 power-domains = <&dispcc_gdsc>;
87
88 clocks = <&gcc_ahb_clk>,
89 <&gcc_axi_clk>,
90 <&dispcc_mdp_clk>;
91 clock-names = "bus", "nrt_bus", "core";
92
93 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-controller;
95 #interrupt-cells = <1>;
96
97 iommus = <&apps_smmu 0x1c00 0x2>;
98
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges;
102
103 display-controller@ae01000 {
104 compatible = "qcom,sm8650-dpu";
105 reg = <0x0ae01000 0x8f000>,
106 <0x0aeb0000 0x2008>;
107 reg-names = "mdp", "vbif";
108
109 clocks = <&gcc_axi_clk>,
110 <&dispcc_ahb_clk>,
111 <&dispcc_mdp_lut_clk>,
112 <&dispcc_mdp_clk>,
113 <&dispcc_mdp_vsync_clk>;
114 clock-names = "nrt_bus",
115 "iface",
116 "lut",
117 "core",
118 "vsync";
119
120 assigned-clocks = <&dispcc_mdp_vsync_clk>;
121 assigned-clock-rates = <19200000>;
122
123 operating-points-v2 = <&mdp_opp_table>;
124 power-domains = <&rpmhpd RPMHPD_MMCX>;
125
126 interrupt-parent = <&mdss>;
127 interrupts = <0>;
128
129 ports {
130 #address-cells = <1>;
131 #size-cells = <0>;
132
133 port@0 {
134 reg = <0>;
135 dpu_intf1_out: endpoint {
136 remote-endpoint = <&dsi0_in>;
137 };
138 };
139
140 port@1 {
141 reg = <1>;
142 dpu_intf2_out: endpoint {
143 remote-endpoint = <&dsi1_in>;
144 };
145 };
146 };
147
148 mdp_opp_table: opp-table {
149 compatible = "operating-points-v2";
150
151 opp-200000000 {
152 opp-hz = /bits/ 64 <200000000>;
153 required-opps = <&rpmhpd_opp_low_svs>;
154 };
155
156 opp-325000000 {
157 opp-hz = /bits/ 64 <325000000>;
158 required-opps = <&rpmhpd_opp_svs>;
159 };
160
161 opp-375000000 {
162 opp-hz = /bits/ 64 <375000000>;
163 required-opps = <&rpmhpd_opp_svs_l1>;
164 };
165
166 opp-514000000 {
167 opp-hz = /bits/ 64 <514000000>;
168 required-opps = <&rpmhpd_opp_nom>;
169 };
170 };
171 };
172
173 dsi@ae94000 {
174 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
175 reg = <0x0ae94000 0x400>;
176 reg-names = "dsi_ctrl";
177
178 interrupt-parent = <&mdss>;
179 interrupts = <4>;
180
181 clocks = <&dispc_byte_clk>,
182 <&dispcc_intf_clk>,
183 <&dispcc_pclk>,
184 <&dispcc_esc_clk>,
185 <&dispcc_ahb_clk>,
186 <&gcc_bus_clk>;
187 clock-names = "byte",
188 "byte_intf",
189 "pixel",
190 "core",
191 "iface",
192 "bus";
193
194 assigned-clocks = <&dispcc_byte_clk>,
195 <&dispcc_pclk>;
196 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
197
198 operating-points-v2 = <&dsi_opp_table>;
199 power-domains = <&rpmhpd RPMHPD_MMCX>;
200
201 phys = <&dsi0_phy>;
202 phy-names = "dsi";
203
204 #address-cells = <1>;
205 #size-cells = <0>;
206
207 ports {
208 #address-cells = <1>;
209 #size-cells = <0>;
210
211 port@0 {
212 reg = <0>;
213 dsi0_in: endpoint {
214 remote-endpoint = <&dpu_intf1_out>;
215 };
216 };
217
218 port@1 {
219 reg = <1>;
220 dsi0_out: endpoint {
221 };
222 };
223 };
224
225 dsi_opp_table: opp-table {
226 compatible = "operating-points-v2";
227
228 opp-187500000 {
229 opp-hz = /bits/ 64 <187500000>;
230 required-opps = <&rpmhpd_opp_low_svs>;
231 };
232
233 opp-300000000 {
234 opp-hz = /bits/ 64 <300000000>;
235 required-opps = <&rpmhpd_opp_svs>;
236 };
237
238 opp-358000000 {
239 opp-hz = /bits/ 64 <358000000>;
240 required-opps = <&rpmhpd_opp_svs_l1>;
241 };
242 };
243 };
244
245 dsi0_phy: phy@ae94400 {
246 compatible = "qcom,sm8650-dsi-phy-4nm";
247 reg = <0x0ae95000 0x200>,
248 <0x0ae95200 0x280>,
249 <0x0ae95500 0x400>;
250 reg-names = "dsi_phy",
251 "dsi_phy_lane",
252 "dsi_pll";
253
254 #clock-cells = <1>;
255 #phy-cells = <0>;
256
257 clocks = <&dispcc_iface_clk>,
258 <&rpmhcc_ref_clk>;
259 clock-names = "iface", "ref";
260 };
261
262 dsi@ae96000 {
263 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
264 reg = <0x0ae96000 0x400>;
265 reg-names = "dsi_ctrl";
266
267 interrupt-parent = <&mdss>;
268 interrupts = <5>;
269
270 clocks = <&dispc_byte_clk>,
271 <&dispcc_intf_clk>,
272 <&dispcc_pclk>,
273 <&dispcc_esc_clk>,
274 <&dispcc_ahb_clk>,
275 <&gcc_bus_clk>;
276 clock-names = "byte",
277 "byte_intf",
278 "pixel",
279 "core",
280 "iface",
281 "bus";
282
283 assigned-clocks = <&dispcc_byte_clk>,
284 <&dispcc_pclk>;
285 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
286
287 operating-points-v2 = <&dsi_opp_table>;
288 power-domains = <&rpmhpd RPMHPD_MMCX>;
289
290 phys = <&dsi1_phy>;
291 phy-names = "dsi";
292
293 #address-cells = <1>;
294 #size-cells = <0>;
295
296 ports {
297 #address-cells = <1>;
298 #size-cells = <0>;
299
300 port@0 {
301 reg = <0>;
302 dsi1_in: endpoint {
303 remote-endpoint = <&dpu_intf2_out>;
304 };
305 };
306
307 port@1 {
308 reg = <1>;
309 dsi1_out: endpoint {
310 };
311 };
312 };
313 };
314
315 dsi1_phy: phy@ae96400 {
316 compatible = "qcom,sm8650-dsi-phy-4nm";
317 reg = <0x0ae97000 0x200>,
318 <0x0ae97200 0x280>,
319 <0x0ae97500 0x400>;
320 reg-names = "dsi_phy",
321 "dsi_phy_lane",
322 "dsi_pll";
323
324 #clock-cells = <1>;
325 #phy-cells = <0>;
326
327 clocks = <&dispcc_iface_clk>,
328 <&rpmhcc_ref_clk>;
329 clock-names = "iface", "ref";
330 };
331 };
332 ...
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