1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm X1E80100 Display MDSS
8
9 maintainers:
10 - Abel Vesa <abel.vesa@linaro.org>
11
12 description:
13 X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces, etc.
15
16 $ref: /schemas/display/msm/mdss-common.yaml#
17
18 properties:
19 compatible:
20 const: qcom,x1e80100-mdss
21
22 clocks:
23 items:
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
27
28 iommus:
29 maxItems: 1
30
31 interconnects:
32 maxItems: 3
33
34 interconnect-names:
35 maxItems: 3
36
37 patternProperties:
38 "^display-controller@[0-9a-f]+$":
39 type: object
40 additionalProperties: true
41 properties:
42 compatible:
43 const: qcom,x1e80100-dpu
44
45 "^displayport-controller@[0-9a-f]+$":
46 type: object
47 additionalProperties: true
48 properties:
49 compatible:
50 const: qcom,x1e80100-dp
51
52 "^phy@[0-9a-f]+$":
53 type: object
54 additionalProperties: true
55 properties:
56 compatible:
57 const: qcom,x1e80100-dp-phy
58
59 required:
60 - compatible
61
62 unevaluatedProperties: false
63
64 examples:
65 - |
66 #include <dt-bindings/clock/qcom,rpmh.h>
67 #include <dt-bindings/interrupt-controller/arm-gic.h>
68 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
69 #include <dt-bindings/phy/phy-qcom-qmp.h>
70 #include <dt-bindings/power/qcom,rpmhpd.h>
71
72 display-subsystem@ae00000 {
73 compatible = "qcom,x1e80100-mdss";
74 reg = <0x0ae00000 0x1000>;
75 reg-names = "mdss";
76
77 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
78 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
79 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
80 interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";
81
82 resets = <&dispcc_core_bcr>;
83
84 power-domains = <&dispcc_gdsc>;
85
86 clocks = <&dispcc_ahb_clk>,
87 <&gcc_disp_hf_axi_clk>,
88 <&dispcc_mdp_clk>;
89 clock-names = "bus", "nrt_bus", "core";
90
91 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
92 interrupt-controller;
93 #interrupt-cells = <1>;
94
95 iommus = <&apps_smmu 0x1c00 0x2>;
96
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
100
101 display-controller@ae01000 {
102 compatible = "qcom,x1e80100-dpu";
103 reg = <0x0ae01000 0x8f000>,
104 <0x0aeb0000 0x2008>;
105 reg-names = "mdp", "vbif";
106
107 clocks = <&gcc_axi_clk>,
108 <&dispcc_ahb_clk>,
109 <&dispcc_mdp_lut_clk>,
110 <&dispcc_mdp_clk>,
111 <&dispcc_mdp_vsync_clk>;
112 clock-names = "nrt_bus",
113 "iface",
114 "lut",
115 "core",
116 "vsync";
117
118 assigned-clocks = <&dispcc_mdp_vsync_clk>;
119 assigned-clock-rates = <19200000>;
120
121 operating-points-v2 = <&mdp_opp_table>;
122 power-domains = <&rpmhpd RPMHPD_MMCX>;
123
124 interrupt-parent = <&mdss>;
125 interrupts = <0>;
126
127 ports {
128 #address-cells = <1>;
129 #size-cells = <0>;
130
131 port@0 {
132 reg = <0>;
133 dpu_intf1_out: endpoint {
134 remote-endpoint = <&dsi0_in>;
135 };
136 };
137
138 port@1 {
139 reg = <1>;
140 dpu_intf2_out: endpoint {
141 remote-endpoint = <&dsi1_in>;
142 };
143 };
144 };
145
146 mdp_opp_table: opp-table {
147 compatible = "operating-points-v2";
148
149 opp-200000000 {
150 opp-hz = /bits/ 64 <200000000>;
151 required-opps = <&rpmhpd_opp_low_svs>;
152 };
153
154 opp-325000000 {
155 opp-hz = /bits/ 64 <325000000>;
156 required-opps = <&rpmhpd_opp_svs>;
157 };
158
159 opp-375000000 {
160 opp-hz = /bits/ 64 <375000000>;
161 required-opps = <&rpmhpd_opp_svs_l1>;
162 };
163
164 opp-514000000 {
165 opp-hz = /bits/ 64 <514000000>;
166 required-opps = <&rpmhpd_opp_nom>;
167 };
168 };
169 };
170
171 displayport-controller@ae90000 {
172 compatible = "qcom,x1e80100-dp";
173 reg = <0 0xae90000 0 0x200>,
174 <0 0xae90200 0 0x200>,
175 <0 0xae90400 0 0x600>,
176 <0 0xae91000 0 0x400>,
177 <0 0xae91400 0 0x400>;
178
179 interrupt-parent = <&mdss>;
180 interrupts = <12>;
181
182 clocks = <&dispcc_mdss_ahb_clk>,
183 <&dispcc_dptx0_aux_clk>,
184 <&dispcc_dptx0_link_clk>,
185 <&dispcc_dptx0_link_intf_clk>,
186 <&dispcc_dptx0_pixel0_clk>;
187 clock-names = "core_iface", "core_aux",
188 "ctrl_link",
189 "ctrl_link_iface",
190 "stream_pixel";
191
192 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
193 <&dispcc_mdss_dptx0_pixel0_clk_src>;
194 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
195 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
196
197 operating-points-v2 = <&mdss_dp0_opp_table>;
198
199 power-domains = <&rpmhpd RPMHPD_MMCX>;
200
201 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
202 phy-names = "dp";
203
204 #sound-dai-cells = <0>;
205
206 ports {
207 #address-cells = <1>;
208 #size-cells = <0>;
209
210 port@0 {
211 reg = <0>;
212
213 mdss_dp0_in: endpoint {
214 remote-endpoint = <&mdss_intf0_out>;
215 };
216 };
217
218 port@1 {
219 reg = <1>;
220
221 mdss_dp0_out: endpoint {
222 };
223 };
224 };
225
226 mdss_dp0_opp_table: opp-table {
227 compatible = "operating-points-v2";
228
229 opp-160000000 {
230 opp-hz = /bits/ 64 <160000000>;
231 required-opps = <&rpmhpd_opp_low_svs>;
232 };
233
234 opp-270000000 {
235 opp-hz = /bits/ 64 <270000000>;
236 required-opps = <&rpmhpd_opp_svs>;
237 };
238
239 opp-540000000 {
240 opp-hz = /bits/ 64 <540000000>;
241 required-opps = <&rpmhpd_opp_svs_l1>;
242 };
243
244 opp-810000000 {
245 opp-hz = /bits/ 64 <810000000>;
246 required-opps = <&rpmhpd_opp_nom>;
247 };
248 };
249 };
250 };
251 ...
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