1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas RZ/G2L Display Unit (DU)
8
9 maintainers:
10 - Biju Das <biju.das.jz@bp.renesas.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
12
13 description: |
14 These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
15 and RZ/V2L SoCs.
16
17 properties:
18 compatible:
19 oneOf:
20 - enum:
21 - renesas,r9a07g043u-du # RZ/G2UL
22 - renesas,r9a07g044-du # RZ/G2{L,LC}
23 - items:
24 - enum:
25 - renesas,r9a07g054-du # RZ/V2L
26 - const: renesas,r9a07g044-du # RZ/G2L fallback
27
28 reg:
29 maxItems: 1
30
31 interrupts:
32 maxItems: 1
33
34 clocks:
35 items:
36 - description: Main clock
37 - description: Register access clock
38 - description: Video clock
39
40 clock-names:
41 items:
42 - const: aclk
43 - const: pclk
44 - const: vclk
45
46 resets:
47 maxItems: 1
48
49 power-domains:
50 maxItems: 1
51
52 ports:
53 $ref: /schemas/graph.yaml#/properties/ports
54 description: |
55 The connections to the DU output video ports are modeled using the OF
56 graph bindings. The number of ports and their assignment are
57 model-dependent. Each port shall have a single endpoint.
58
59 patternProperties:
60 "^port@[0-1]$":
61 $ref: /schemas/graph.yaml#/properties/port
62 unevaluatedProperties: false
63
64 unevaluatedProperties: false
65
66 renesas,vsps:
67 $ref: /schemas/types.yaml#/definitions/phandle-array
68 items:
69 items:
70 - description: phandle to VSP instance that serves the DU channel
71 - description: Channel index identifying the LIF instance in that VSP
72 description:
73 A list of phandle and channel index tuples to the VSPs that handle the
74 memory interfaces for the DU channels.
75
76 required:
77 - compatible
78 - reg
79 - interrupts
80 - clocks
81 - clock-names
82 - resets
83 - power-domains
84 - ports
85 - renesas,vsps
86
87 additionalProperties: false
88
89 allOf:
90 - if:
91 properties:
92 compatible:
93 contains:
94 const: renesas,r9a07g043u-du
95 then:
96 properties:
97 ports:
98 properties:
99 port@0:
100 description: DPI
101
102 required:
103 - port@0
104 else:
105 properties:
106 ports:
107 properties:
108 port@0:
109 description: DSI
110 port@1:
111 description: DPI
112
113 required:
114 - port@0
115 - port@1
116
117 examples:
118 # RZ/G2L DU
119 - |
120 #include <dt-bindings/clock/r9a07g044-cpg.h>
121 #include <dt-bindings/interrupt-controller/arm-gic.h>
122
123 display@10890000 {
124 compatible = "renesas,r9a07g044-du";
125 reg = <0x10890000 0x10000>;
126 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
128 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
129 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
130 clock-names = "aclk", "pclk", "vclk";
131 resets = <&cpg R9A07G044_LCDC_RESET_N>;
132 power-domains = <&cpg>;
133
134 renesas,vsps = <&vspd0 0>;
135
136 ports {
137 #address-cells = <1>;
138 #size-cells = <0>;
139
140 port@0 {
141 reg = <0>;
142 endpoint {
143 remote-endpoint = <&dsi0_in>;
144 };
145 };
146 port@1 {
147 reg = <1>;
148 };
149 };
150 };
151
152 ...
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