1 STMicroelectronics stih4xx platforms
2
3 - sti-vtg: video timing generator
4 Required properties:
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
7 Optional properties:
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
10
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
12 Required properties:
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
19 order.
20
21 - sti-display-subsystem: Master device for DRM sub-components
22 This device must be the parent of all the sub-components and is responsible
23 of bind them.
24 Required properties:
25 - compatible: "st,sti-display-subsystem"
26 - ranges: to allow probing of subdevices
27
28 - sti-compositor: frame compositor engine
29 must be a child of sti-display-subsystem
30 Required properties:
31 - compatible: "st,stih<chip>-compositor"
32 - reg: Physical base address of the IP registers and length of memory mapped region.
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
37 order.
38 - resets: resets to be used by the device
39 See ../reset/reset.txt for details.
40 - reset-names: names of the resets listed in resets property in the same
41 order.
42 - st,vtg: phandle(s) on vtg device (main and aux) nodes.
43
44 - sti-tvout: video out hardware block
45 must be a child of sti-display-subsystem
46 Required properties:
47 - compatible: "st,stih<chip>-tvout"
48 - reg: Physical base address of the IP registers and length of memory mapped region.
49 - reg-names: names of the mapped memory regions listed in regs property in
50 the same order.
51 - resets: resets to be used by the device
52 See ../reset/reset.txt for details.
53 - reset-names: names of the resets listed in resets property in the same
54 order.
55
56 - sti-hdmi: hdmi output block
57 must be a child of sti-display-subsystem
58 Required properties:
59 - compatible: "st,stih<chip>-hdmi";
60 - reg: Physical base address of the IP registers and length of memory mapped region.
61 - reg-names: names of the mapped memory regions listed in regs property in
62 the same order.
63 - interrupts : HDMI interrupt number to the CPU.
64 - interrupt-names: names of the interrupts listed in interrupts property in
65 the same order
66 - clocks: from common clock binding: handle hardware IP needed clocks, the
67 number of clocks may depend of the SoC type.
68 - clock-names: names of the clocks listed in clocks property in the same
69 order.
70 - ddc: phandle of an I2C controller used for DDC EDID probing
71
72 sti-hda:
73 Required properties:
74 must be a child of sti-display-subsystem
75 - compatible: "st,stih<chip>-hda"
76 - reg: Physical base address of the IP registers and length of memory mapped region.
77 - reg-names: names of the mapped memory regions listed in regs property in
78 the same order.
79 - clocks: from common clock binding: handle hardware IP needed clocks, the
80 number of clocks may depend of the SoC type.
81 See ../clocks/clock-bindings.txt for details.
82 - clock-names: names of the clocks listed in clocks property in the same
83 order.
84
85 sti-dvo:
86 Required properties:
87 must be a child of sti-display-subsystem
88 - compatible: "st,stih<chip>-dvo"
89 - reg: Physical base address of the IP registers and length of memory mapped region.
90 - reg-names: names of the mapped memory regions listed in regs property in
91 the same order.
92 - clocks: from common clock binding: handle hardware IP needed clocks, the
93 number of clocks may depend of the SoC type.
94 See ../clocks/clock-bindings.txt for details.
95 - clock-names: names of the clocks listed in clocks property in the same
96 order.
97 - pinctrl-0: pin control handle
98 - pinctrl-names: names of the pin control states to use
99 - sti,panel: phandle of the panel connected to the DVO output
100
101 sti-hqvdp:
102 must be a child of sti-display-subsystem
103 Required properties:
104 - compatible: "st,stih<chip>-hqvdp"
105 - reg: Physical base address of the IP registers and length of memory mapped region.
106 - clocks: from common clock binding: handle hardware IP needed clocks, the
107 number of clocks may depend of the SoC type.
108 See ../clocks/clock-bindings.txt for details.
109 - clock-names: names of the clocks listed in clocks property in the same
110 order.
111 - resets: resets to be used by the device
112 See ../reset/reset.txt for details.
113 - reset-names: names of the resets listed in resets property in the same
114 order.
115 - st,vtg: phandle on vtg main device node.
116
117 Example:
118
119 / {
120 ...
121
122 vtg_main_slave: sti-vtg-main-slave@fe85a800 {
123 compatible = "st,vtg";
124 reg = <0xfe85A800 0x300>;
125 interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
126 };
127
128 vtg_main: sti-vtg-main-master@fd348000 {
129 compatible = "st,vtg";
130 reg = <0xfd348000 0x400>;
131 st,slave = <&vtg_main_slave>;
132 };
133
134 vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
135 compatible = "st,vtg";
136 reg = <0xfe858200 0x300>;
137 interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>;
138 };
139
140 vtg_aux: sti-vtg-aux-master@fd348400 {
141 compatible = "st,vtg";
142 reg = <0xfd348400 0x400>;
143 st,slave = <&vtg_aux_slave>;
144 };
145
146
147 sti-vtac-rx-main@fee82800 {
148 compatible = "st,vtac-main";
149 reg = <0xfee82800 0x200>;
150 clock-names = "vtac";
151 clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
152 };
153
154 sti-vtac-rx-aux@fee82a00 {
155 compatible = "st,vtac-aux";
156 reg = <0xfee82a00 0x200>;
157 clock-names = "vtac";
158 clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
159 };
160
161 sti-vtac-tx-main@fd349000 {
162 compatible = "st,vtac-main";
163 reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
164 clock-names = "vtac";
165 clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
166 };
167
168 sti-vtac-tx-aux@fd349200 {
169 compatible = "st,vtac-aux";
170 reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
171 clock-names = "vtac";
172 clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
173 };
174
175 sti-display-subsystem {
176 compatible = "st,sti-display-subsystem";
177 ranges;
178
179 sti-compositor@fd340000 {
180 compatible = "st,stih416-compositor";
181 reg = <0xfd340000 0x1000>;
182 clock-names = "compo_main", "compo_aux",
183 "pix_main", "pix_aux";
184 clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
185 <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
186 reset-names = "compo-main", "compo-aux";
187 resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
188 st,vtg = <&vtg_main>, <&vtg_aux>;
189 };
190
191 sti-tvout@fe000000 {
192 compatible = "st,stih416-tvout";
193 reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
194 reg-names = "tvout-reg", "hda-reg", "syscfg";
195 reset-names = "tvout";
196 resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
197 };
198
199 sti-hdmi@fe85c000 {
200 compatible = "st,stih416-hdmi";
201 reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
202 reg-names = "hdmi-reg", "syscfg";
203 interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
204 interrupt-names = "irq";
205 clock-names = "pix", "tmds", "phy", "audio";
206 clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
207 };
208
209 sti-hda@fe85a000 {
210 compatible = "st,stih416-hda";
211 reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
212 reg-names = "hda-reg", "video-dacs-ctrl";
213 clock-names = "pix", "hddac";
214 clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
215 };
216
217 sti-dvo@8d00400 {
218 compatible = "st,stih407-dvo";
219 reg = <0x8d00400 0x200>;
220 reg-names = "dvo-reg";
221 clock-names = "dvo_pix", "dvo",
222 "main_parent", "aux_parent";
223 clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>,
224 <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_dvo>;
227 sti,panel = <&panel_dvo>;
228 };
229
230 sti-hqvdp@9c000000 {
231 compatible = "st,stih407-hqvdp";
232 reg = <0x9C00000 0x100000>;
233 clock-names = "hqvdp", "pix_main";
234 clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
235 reset-names = "hqvdp";
236 resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
237 st,vtg = <&vtg_main>;
238 };
239 };
240 ...
241 };
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