1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NVIDIA Tegra Display Serial Interface
8
9 maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13 properties:
14 compatible:
15 oneOf:
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
20 - nvidia,tegra124-dsi
21 - nvidia,tegra210-dsi
22 - nvidia,tegra186-dsi
23
24 - items:
25 - const: nvidia,tegra132-dsi
26 - const: nvidia,tegra124-dsi
27
28 reg:
29 maxItems: 1
30
31 interrupts:
32 maxItems: 1
33
34 clocks:
35 minItems: 2
36 maxItems: 3
37
38 clock-names:
39 minItems: 2
40 maxItems: 3
41
42 resets:
43 items:
44 - description: module reset
45
46 reset-names:
47 items:
48 - const: dsi
49
50 operating-points-v2: true
51
52 power-domains:
53 maxItems: 1
54
55 avdd-dsi-csi-supply:
56 description: phandle of a supply that powers the DSI controller
57
58 nvidia,mipi-calibrate:
59 description: Should contain a phandle and a specifier specifying
60 which pads are used by this DSI output and need to be
61 calibrated. See nvidia,tegra114-mipi.yaml for details.
62 $ref: /schemas/types.yaml#/definitions/phandle-array
63
64 nvidia,ddc-i2c-bus:
65 description: phandle of an I2C controller used for DDC EDID
66 probing
67 $ref: /schemas/types.yaml#/definitions/phandle
68
69 nvidia,hpd-gpio:
70 description: specifies a GPIO used for hotplug detection
71 maxItems: 1
72
73 nvidia,edid:
74 description: supplies a binary EDID blob
75 $ref: /schemas/types.yaml#/definitions/uint8-array
76
77 nvidia,panel:
78 description: phandle of a display panel
79 $ref: /schemas/types.yaml#/definitions/phandle
80
81 nvidia,ganged-mode:
82 description: contains a phandle to a second DSI controller to
83 gang up with in order to support up to 8 data lanes
84 $ref: /schemas/types.yaml#/definitions/phandle
85
86 allOf:
87 - $ref: ../dsi-controller.yaml#
88 - if:
89 properties:
90 compatible:
91 contains:
92 enum:
93 - nvidia,tegra20-dsi
94 - nvidia,tegra30-dsi
95 then:
96 properties:
97 clocks:
98 items:
99 - description: DSI module clock
100 - description: input for the pixel clock
101
102 clock-names:
103 items:
104 - const: dsi
105 - const: parent
106 else:
107 properties:
108 clocks:
109 items:
110 - description: DSI module clock
111 - description: low-power module clock
112 - description: input for the pixel clock
113
114 clock-names:
115 items:
116 - const: dsi
117 - const: lp
118 - const: parent
119
120 - if:
121 properties:
122 compatible:
123 contains:
124 const: nvidia,tegra186-dsi
125 then:
126 required:
127 - interrupts
128
129 unevaluatedProperties: false
130
131 required:
132 - compatible
133 - reg
134 - clocks
135 - clock-names
136 - resets
137 - reset-names
138
139 examples:
140 - |
141 #include <dt-bindings/clock/tegra186-clock.h>
142 #include <dt-bindings/interrupt-controller/arm-gic.h>
143 #include <dt-bindings/power/tegra186-powergate.h>
144 #include <dt-bindings/reset/tegra186-reset.h>
145
146 dsi@15300000 {
147 compatible = "nvidia,tegra186-dsi";
148 reg = <0x15300000 0x10000>;
149 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&bpmp TEGRA186_CLK_DSI>,
151 <&bpmp TEGRA186_CLK_DSIA_LP>,
152 <&bpmp TEGRA186_CLK_PLLD>;
153 clock-names = "dsi", "lp", "parent";
154 resets = <&bpmp TEGRA186_RESET_DSI>;
155 reset-names = "dsi";
156
157 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
158 };
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