1 Texas Instruments OMAP5 Display Subsystem 2 ========================================= 3 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 5 description about OMAP Display Subsystem bindings. 6 7 DSS Core 8 -------- 9 10 Required properties: 11 - compatible: "ti,omap5-dss" 12 - reg: address and length of the register space 13 - ti,hwmods: "dss_core" 14 - clocks: handle to fclk 15 - clock-names: "fck" 16 17 Required nodes: 18 - DISPC 19 20 Optional nodes: 21 - DSS Submodules: RFBI, DSI, HDMI 22 - Video port for DPI output 23 24 DPI Endpoint required properties: 25 - data-lines: number of lines used 26 27 28 DISPC 29 ----- 30 31 Required properties: 32 - compatible: "ti,omap5-dispc" 33 - reg: address and length of the register space 34 - ti,hwmods: "dss_dispc" 35 - interrupts: the DISPC interrupt 36 - clocks: handle to fclk 37 - clock-names: "fck" 38 39 Optional properties: 40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit 41 in bytes per second 42 43 44 RFBI 45 ---- 46 47 Required properties: 48 - compatible: "ti,omap5-rfbi" 49 - reg: address and length of the register space 50 - ti,hwmods: "dss_rfbi" 51 - clocks: handles to fclk and iclk 52 - clock-names: "fck", "ick" 53 54 Optional nodes: 55 - Video port for RFBI output 56 - RFBI controlled peripherals 57 58 59 DSI 60 --- 61 62 Required properties: 63 - compatible: "ti,omap5-dsi" 64 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll' 65 - reg-names: "proto", "phy", "pll" 66 - interrupts: the DSI interrupt line 67 - ti,hwmods: "dss_dsi1" or "dss_dsi2" 68 - vdd-supply: power supply for DSI 69 - clocks: handles to fclk and pll clock 70 - clock-names: "fck", "sys_clk" 71 72 Optional nodes: 73 - Video port for DSI output 74 - DSI controlled peripherals 75 76 DSI Endpoint required properties: 77 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-, 78 DATA1+, DATA1-, ... 79 80 81 HDMI 82 ---- 83 84 Required properties: 85 - compatible: "ti,omap5-hdmi" 86 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', 87 'core' 88 - reg-names: "wp", "pll", "phy", "core" 89 - interrupts: the HDMI interrupt line 90 - ti,hwmods: "dss_hdmi" 91 - vdda-supply: vdda power supply 92 - clocks: handles to fclk and pll clock 93 - clock-names: "fck", "sys_clk" 94 95 Optional nodes: 96 - Video port for HDMI output 97 98 HDMI Endpoint optional properties: 99 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, 100 D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)
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