1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
8
9 maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12 allOf:
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: dma-controller.yaml#
15
16 # We need a select here so we don't match all nodes with 'arm,primecell'
17 select:
18 properties:
19 compatible:
20 contains:
21 enum:
22 - arm,pl080
23 - arm,pl081
24 required:
25 - compatible
26
27 properties:
28 compatible:
29 oneOf:
30 - items:
31 - enum:
32 - arm,pl080
33 - arm,pl081
34 - const: arm,primecell
35 - items:
36 - const: faraday,ftdma020
37 - const: arm,pl080
38 - const: arm,primecell
39
40 reg:
41 maxItems: 1
42 description: Address range of the PL08x registers
43
44 interrupts:
45 minItems: 1
46 description: The PL08x interrupt number
47
48 clocks:
49 minItems: 1
50 description: The clock running the IP core clock
51
52 clock-names:
53 maxItems: 1
54
55 lli-bus-interface-ahb1:
56 type: boolean
57 description: if AHB master 1 is eligible for fetching LLIs
58
59 lli-bus-interface-ahb2:
60 type: boolean
61 description: if AHB master 2 is eligible for fetching LLIs
62
63 mem-bus-interface-ahb1:
64 type: boolean
65 description: if AHB master 1 is eligible for fetching memory contents
66
67 mem-bus-interface-ahb2:
68 type: boolean
69 description: if AHB master 2 is eligible for fetching memory contents
70
71 memcpy-burst-size:
72 $ref: /schemas/types.yaml#/definitions/uint32
73 enum:
74 - 1
75 - 4
76 - 8
77 - 16
78 - 32
79 - 64
80 - 128
81 - 256
82 description: the size of the bursts for memcpy
83
84 memcpy-bus-width:
85 $ref: /schemas/types.yaml#/definitions/uint32
86 enum:
87 - 8
88 - 16
89 - 32
90 - 64
91 description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits
92
93 resets:
94 maxItems: 1
95
96 required:
97 - reg
98 - interrupts
99 - clocks
100 - clock-names
101 - "#dma-cells"
102
103 unevaluatedProperties: false
104
105 examples:
106 - |
107 dmac0: dma-controller@10130000 {
108 compatible = "arm,pl080", "arm,primecell";
109 reg = <0x10130000 0x1000>;
110 interrupt-parent = <&vica>;
111 interrupts = <15>;
112 clocks = <&hclkdma0>;
113 clock-names = "apb_pclk";
114 lli-bus-interface-ahb1;
115 lli-bus-interface-ahb2;
116 mem-bus-interface-ahb2;
117 memcpy-burst-size = <256>;
118 memcpy-bus-width = <32>;
119 #dma-cells = <2>;
120 };
121 - |
122 #include <dt-bindings/interrupt-controller/irq.h>
123 #include <dt-bindings/reset/cortina,gemini-reset.h>
124 #include <dt-bindings/clock/cortina,gemini-clock.h>
125 dma-controller@67000000 {
126 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
127 /* Faraday Technology FTDMAC020 variant */
128 arm,primecell-periphid = <0x0003b080>;
129 reg = <0x67000000 0x1000>;
130 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
131 resets = <&syscon GEMINI_RESET_DMAC>;
132 clocks = <&syscon GEMINI_CLK_AHB>;
133 clock-names = "apb_pclk";
134 /* Bus interface AHB1 (AHB0) is totally tilted */
135 lli-bus-interface-ahb2;
136 mem-bus-interface-ahb2;
137 memcpy-burst-size = <256>;
138 memcpy-bus-width = <32>;
139 #dma-cells = <2>;
140 };
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