1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek UART APDMA controller
8
9 maintainers:
10 - Long Cheng <long.cheng@mediatek.com>
11
12 description: |
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
15
16 allOf:
17 - $ref: dma-controller.yaml#
18
19 properties:
20 compatible:
21 oneOf:
22 - items:
23 - enum:
24 - mediatek,mt2712-uart-dma
25 - mediatek,mt6795-uart-dma
26 - mediatek,mt8365-uart-dma
27 - mediatek,mt8516-uart-dma
28 - const: mediatek,mt6577-uart-dma
29 - enum:
30 - mediatek,mt6577-uart-dma
31
32 reg:
33 minItems: 1
34 maxItems: 16
35
36 interrupts:
37 description: |
38 TX, RX interrupt lines for each UART APDMA channel
39 minItems: 1
40 maxItems: 16
41
42 clocks:
43 description: Must contain one entry for the APDMA main clock
44 maxItems: 1
45
46 clock-names:
47 const: apdma
48
49 "#dma-cells":
50 const: 1
51 description: |
52 The first cell specifies the UART APDMA channel number
53
54 dma-requests:
55 description: |
56 Number of virtual channels of the UART APDMA controller
57 maximum: 16
58
59 mediatek,dma-33bits:
60 type: boolean
61 description: Enable 33-bits UART APDMA support
62
63 required:
64 - compatible
65 - reg
66 - interrupts
67
68 additionalProperties: false
69
70 if:
71 not:
72 required:
73 - dma-requests
74 then:
75 properties:
76 interrupts:
77 maxItems: 8
78 reg:
79 maxItems: 8
80
81 examples:
82 - |
83 #include <dt-bindings/interrupt-controller/arm-gic.h>
84 #include <dt-bindings/clock/mt2712-clk.h>
85 soc {
86 #address-cells = <2>;
87 #size-cells = <2>;
88
89 apdma: dma-controller@11000400 {
90 compatible = "mediatek,mt2712-uart-dma",
91 "mediatek,mt6577-uart-dma";
92 reg = <0 0x11000400 0 0x80>,
93 <0 0x11000480 0 0x80>,
94 <0 0x11000500 0 0x80>,
95 <0 0x11000580 0 0x80>,
96 <0 0x11000600 0 0x80>,
97 <0 0x11000680 0 0x80>,
98 <0 0x11000700 0 0x80>,
99 <0 0x11000780 0 0x80>,
100 <0 0x11000800 0 0x80>,
101 <0 0x11000880 0 0x80>,
102 <0 0x11000900 0 0x80>,
103 <0 0x11000980 0 0x80>;
104 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
105 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
106 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
107 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
108 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
109 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
110 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
111 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
112 <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
113 <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
114 <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
115 <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
116 dma-requests = <12>;
117 clocks = <&pericfg CLK_PERI_AP_DMA>;
118 clock-names = "apdma";
119 mediatek,dma-33bits;
120 #dma-cells = <1>;
121 };
122 };
123
124 ...
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