1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NVIDIA Tegra GPC DMA Controller
8
9 description: |
10 The Tegra General Purpose Central (GPC) DMA controller is used for faster
11 data transfers between memory to memory, memory to device and device to
12 memory.
13
14 maintainers:
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Rajesh Gumasta <rgumasta@nvidia.com>
17
18 allOf:
19 - $ref: dma-controller.yaml#
20
21 properties:
22 compatible:
23 oneOf:
24 - const: nvidia,tegra186-gpcdma
25 - items:
26 - enum:
27 - nvidia,tegra234-gpcdma
28 - nvidia,tegra194-gpcdma
29 - const: nvidia,tegra186-gpcdma
30
31 "#dma-cells":
32 const: 1
33
34 reg:
35 maxItems: 1
36
37 interrupts:
38 description:
39 Should contain all of the per-channel DMA interrupts in
40 ascending order with respect to the DMA channel index.
41 minItems: 1
42 maxItems: 32
43
44 resets:
45 maxItems: 1
46
47 reset-names:
48 const: gpcdma
49
50 iommus:
51 maxItems: 1
52
53 dma-coherent: true
54
55 dma-channel-mask:
56 maxItems: 1
57
58 required:
59 - compatible
60 - reg
61 - interrupts
62 - resets
63 - reset-names
64 - "#dma-cells"
65 - iommus
66 - dma-channel-mask
67
68 additionalProperties: false
69
70 examples:
71 - |
72 #include <dt-bindings/interrupt-controller/arm-gic.h>
73 #include <dt-bindings/memory/tegra186-mc.h>
74 #include <dt-bindings/reset/tegra186-reset.h>
75
76 dma-controller@2600000 {
77 compatible = "nvidia,tegra186-gpcdma";
78 reg = <0x2600000 0x210000>;
79 resets = <&bpmp TEGRA186_RESET_GPCDMA>;
80 reset-names = "gpcdma";
81 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
112 #dma-cells = <1>;
113 iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
114 dma-coherent;
115 dma-channel-mask = <0xfffffffe>;
116 };
117 ...
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