1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
8
9 maintainers:
10 - Biju Das <biju.das.jz@bp.renesas.com>
11
12 allOf:
13 - $ref: dma-controller.yaml#
14
15 properties:
16 compatible:
17 items:
18 - enum:
19 - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
20 - renesas,r9a07g044-dmac # RZ/G2{L,LC}
21 - renesas,r9a07g054-dmac # RZ/V2L
22 - renesas,r9a08g045-dmac # RZ/G3S
23 - const: renesas,rz-dmac
24
25 reg:
26 items:
27 - description: Control and channel register block
28 - description: DMA extended resource selector block
29
30 interrupts:
31 maxItems: 17
32
33 interrupt-names:
34 items:
35 - const: error
36 - const: ch0
37 - const: ch1
38 - const: ch2
39 - const: ch3
40 - const: ch4
41 - const: ch5
42 - const: ch6
43 - const: ch7
44 - const: ch8
45 - const: ch9
46 - const: ch10
47 - const: ch11
48 - const: ch12
49 - const: ch13
50 - const: ch14
51 - const: ch15
52
53 clocks:
54 items:
55 - description: DMA main clock
56 - description: DMA register access clock
57
58 clock-names:
59 items:
60 - const: main
61 - const: register
62
63 '#dma-cells':
64 const: 1
65 description:
66 The cell specifies the encoded MID/RID values of the DMAC port
67 connected to the DMA client and the slave channel configuration
68 parameters.
69 bits[0:9] - Specifies MID/RID value
70 bit[10] - Specifies DMA request high enable (HIEN)
71 bit[11] - Specifies DMA request detection type (LVL)
72 bits[12:14] - Specifies DMAACK output mode (AM)
73 bit[15] - Specifies Transfer Mode (TM)
74
75 dma-channels:
76 const: 16
77
78 power-domains:
79 maxItems: 1
80
81 resets:
82 items:
83 - description: Reset for DMA ARESETN reset terminal
84 - description: Reset for DMA RST_ASYNC reset terminal
85
86 reset-names:
87 items:
88 - const: arst
89 - const: rst_async
90
91 required:
92 - compatible
93 - reg
94 - interrupts
95 - interrupt-names
96 - clocks
97 - clock-names
98 - '#dma-cells'
99 - dma-channels
100 - power-domains
101 - resets
102 - reset-names
103
104 additionalProperties: false
105
106 examples:
107 - |
108 #include <dt-bindings/interrupt-controller/arm-gic.h>
109 #include <dt-bindings/clock/r9a07g044-cpg.h>
110
111 dmac: dma-controller@11820000 {
112 compatible = "renesas,r9a07g044-dmac",
113 "renesas,rz-dmac";
114 reg = <0x11820000 0x10000>,
115 <0x11830000 0x10000>;
116 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
117 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
118 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
119 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
120 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
121 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
122 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
123 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
124 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
125 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
126 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
127 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
128 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
129 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
130 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
131 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
132 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
133 interrupt-names = "error",
134 "ch0", "ch1", "ch2", "ch3",
135 "ch4", "ch5", "ch6", "ch7",
136 "ch8", "ch9", "ch10", "ch11",
137 "ch12", "ch13", "ch14", "ch15";
138 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
139 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
140 clock-names = "main", "register";
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G044_DMAC_ARESETN>,
143 <&cpg R9A07G044_DMAC_RST_ASYNC>;
144 reset-names = "arst", "rst_async";
145 #dma-cells = <1>;
146 dma-channels = <16>;
147 };
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