1 Texas Instruments eDMA
2
3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
7
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
10
11 Required properties:
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
15 AM33xx and AM43xx SoCs.
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
17 channel controller(s) on 66AK2G.
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
19 number and the second is the TC the channel is serviced on.
20 - reg: Memory map of eDMA CC
21 - reg-names: "edma3_cc"
22 - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
23 - interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
24 - ti,tptcs: List of TPTCs associated with the eDMA in the following form:
25 <&tptc_phandle TC_priority_number>. The highest priority is 0.
26
27 SoC-specific Required properties:
28 --------------------------------
29 The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
30 - ti,hwmods: Name of the hwmods associated to the eDMA CC.
31
32 The following are mandatory properties for 66AK2G SoCs only:
33 - power-domains:Should contain a phandle to a PM domain provider node
34 and an args specifier containing the device id
35 value. This property is as per the binding,
36 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
37
38 Optional properties:
39 -------------------
40 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
41 these channels will be SW triggered channels. See example.
42 - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
43 the driver, they are allocated to be used by for example the
44 DSP. See example.
45 - dma-channel-mask: Mask of usable channels.
46 Single uint32 for EDMA with 32 channels, array of two uint32 for
47 EDMA with 64 channels. See example and
48 Documentation/devicetree/bindings/dma/dma-common.yaml
49
50
51 ------------------------------------------------------------------------------
52 eDMA3 Transfer Controller
53
54 Required properties:
55 --------------------
56 - compatible: Should be:
57 - "ti,edma3-tptc" for the transfer controller(s) on OMAP,
58 AM33xx and AM43xx SoCs.
59 - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
60 transfer controller(s) on 66AK2G.
61 - reg: Memory map of eDMA TC
62 - interrupts: Interrupt number for TCerrint.
63
64 SoC-specific Required properties:
65 --------------------------------
66 The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
67 - ti,hwmods: Name of the hwmods associated to the eDMA TC.
68
69 The following are mandatory properties for 66AK2G SoCs only:
70 - power-domains:Should contain a phandle to a PM domain provider node
71 and an args specifier containing the device id
72 value. This property is as per the binding,
73 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
74
75 Optional properties:
76 -------------------
77 - interrupt-names: "edma3_tcerrint"
78
79 ------------------------------------------------------------------------------
80 Examples:
81
82 1.
83 edma: edma@49000000 {
84 compatible = "ti,edma3-tpcc";
85 ti,hwmods = "tpcc";
86 reg = <0x49000000 0x10000>;
87 reg-names = "edma3_cc";
88 interrupts = <12 13 14>;
89 interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
90 dma-requests = <64>;
91 #dma-cells = <2>;
92
93 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
94
95 /* Channel 20 and 21 is allocated for memcpy */
96 ti,edma-memcpy-channels = <20 21>;
97 /* The following PaRAM slots are reserved: 35-44 and 100-109 */
98 ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
99 /* The following channels are reserved: 35-44 */
100 dma-channel-mask = <0xffffffff /* Channel 0-31 */
101 0xffffe007>; /* Channel 32-63 */
102 };
103
104 edma_tptc0: tptc@49800000 {
105 compatible = "ti,edma3-tptc";
106 ti,hwmods = "tptc0";
107 reg = <0x49800000 0x100000>;
108 interrupts = <112>;
109 interrupt-names = "edm3_tcerrint";
110 };
111
112 edma_tptc1: tptc@49900000 {
113 compatible = "ti,edma3-tptc";
114 ti,hwmods = "tptc1";
115 reg = <0x49900000 0x100000>;
116 interrupts = <113>;
117 interrupt-names = "edm3_tcerrint";
118 };
119
120 edma_tptc2: tptc@49a00000 {
121 compatible = "ti,edma3-tptc";
122 ti,hwmods = "tptc2";
123 reg = <0x49a00000 0x100000>;
124 interrupts = <114>;
125 interrupt-names = "edm3_tcerrint";
126 };
127
128 sham: sham@53100000 {
129 compatible = "ti,omap4-sham";
130 ti,hwmods = "sham";
131 reg = <0x53100000 0x200>;
132 interrupts = <109>;
133 /* DMA channel 36 executed on eDMA TC0 - low priority queue */
134 dmas = <&edma 36 0>;
135 dma-names = "rx";
136 };
137
138 mcasp0: mcasp@48038000 {
139 compatible = "ti,am33xx-mcasp-audio";
140 ti,hwmods = "mcasp0";
141 reg = <0x48038000 0x2000>,
142 <0x46000000 0x400000>;
143 reg-names = "mpu", "dat";
144 interrupts = <80>, <81>;
145 interrupt-names = "tx", "rx";
146 /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
147 dmas = <&edma 8 2>,
148 <&edma 9 2>;
149 dma-names = "tx", "rx";
150 };
151
152 2.
153 edma1: edma@2728000 {
154 compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
155 reg = <0x02728000 0x8000>;
156 reg-names = "edma3_cc";
157 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
158 <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
159 <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
160 interrupt-names = "edma3_ccint", "emda3_mperr",
161 "edma3_ccerrint";
162 dma-requests = <64>;
163 #dma-cells = <2>;
164
165 ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
166
167 /*
168 * memcpy is disabled, can be enabled with:
169 * ti,edma-memcpy-channels = <12 13 14 15>;
170 * for example.
171 */
172
173 power-domains = <&k2g_pds 0x4f>;
174 };
175
176 edma1_tptc0: tptc@27b0000 {
177 compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
178 reg = <0x027b0000 0x400>;
179 power-domains = <&k2g_pds 0x4f>;
180 };
181
182 edma1_tptc1: tptc@27b8000 {
183 compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
184 reg = <0x027b8000 0x400>;
185 power-domains = <&k2g_pds 0x4f>;
186 };
187
188 mmc0: mmc@23000000 {
189 compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
190 reg = <0x23000000 0x400>;
191 interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
192 dmas = <&edma1 24 0>, <&edma1 25 0>;
193 dma-names = "tx", "rx";
194 bus-width = <4>;
195 ti,needs-special-reset;
196 no-1-8-v;
197 max-frequency = <96000000>;
198 power-domains = <&k2g_pds 0xb>;
199 clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
200 clock-names = "fck", "mmchsdb_fck";
201 };
202
203 ------------------------------------------------------------------------------
204 DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
205 binding.
206
207 Required properties:
208 - compatible : "ti,edma3"
209 - #dma-cells: Should be set to <1>
210 Clients should use a single channel number per DMA request.
211 - reg: Memory map for accessing module
212 - interrupts: Exactly 3 interrupts need to be specified in the order:
213 1. Transfer completion interrupt.
214 2. Memory protection interrupt.
215 3. Error interrupt.
216 Optional properties:
217 - ti,hwmods: Name of the hwmods associated to the EDMA
218 - ti,edma-xbar-event-map: Crossbar event to channel map
219
220 Deprecated properties:
221 Listed here in case one wants to boot an old kernel with new DTB. These
222 properties might need to be added to the new DTS files.
223 - ti,edma-regions: Number of regions
224 - ti,edma-slots: Number of slots
225 - dma-channels: Specify total DMA channels per CC
226
227 Example:
228
229 edma: edma@49000000 {
230 reg = <0x49000000 0x10000>;
231 interrupt-parent = <&intc>;
232 interrupts = <12 13 14>;
233 compatible = "ti,edma3";
234 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
235 #dma-cells = <1>;
236 ti,edma-xbar-event-map = /bits/ 16 <1 12
237 2 13>;
238 };
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