1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019 Linaro Ltd.
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7
8 title: Intel IXP4xx Network Processing Engine
9
10 maintainers:
11 - Linus Walleij <linus.walleij@linaro.org>
12
13 description: |
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
15 processor that can load a firmware to perform offloading of networking
16 and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
17 on the IXP4xx platform. All IXP4xx platforms have three NPEs at
18 consecutive memory locations. They are all included in the same
19 device node since they are not independent of each other.
20
21 properties:
22 compatible:
23 oneOf:
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
26
27 reg:
28 items:
29 - description: NPE0 (NPE-A) register range
30 - description: NPE1 (NPE-B) register range
31 - description: NPE2 (NPE-C) register range
32
33 crypto:
34 $ref: /schemas/crypto/intel,ixp4xx-crypto.yaml#
35 type: object
36 description: Optional node for the embedded crypto engine, the node
37 should be named with the instance number of the NPE engine used for
38 the crypto engine.
39
40 "#address-cells":
41 const: 1
42
43 "#size-cells":
44 const: 0
45
46 patternProperties:
47 hss@[0-9]+$:
48 $ref: /schemas/net/intel,ixp4xx-hss.yaml#
49 type: object
50 description: Optional node for the High Speed Serial link (HSS), the
51 node should be named with the instance number of the NPE engine
52 used for the HSS.
53
54 required:
55 - compatible
56 - reg
57
58 additionalProperties: false
59
60 examples:
61 - |
62 #include <dt-bindings/gpio/gpio.h>
63
64 npe: npe@c8006000 {
65 compatible = "intel,ixp4xx-network-processing-engine";
66 reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 hss@0 {
71 compatible = "intel,ixp4xx-hss";
72 reg = <0>;
73 intel,npe-handle = <&npe 0>;
74 intel,queue-chl-rxtrig = <&qmgr 12>;
75 intel,queue-chl-txready = <&qmgr 34>;
76 intel,queue-pkt-rx = <&qmgr 13>;
77 intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
78 intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
79 intel,queue-pkt-txdone = <&qmgr 22>;
80 cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
81 rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
82 dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
83 dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
84 clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
85 };
86
87 crypto {
88 compatible = "intel,ixp4xx-crypto";
89 intel,npe-handle = <&npe 2>;
90 queue-rx = <&qmgr 30>;
91 queue-txready = <&qmgr 29>;
92 };
93 };
94 ...
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