1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Xilinx Zynq FPGA Manager
8
9 maintainers:
10 - Michal Simek <michal.simek@amd.com>
11
12 properties:
13 compatible:
14 const: xlnx,zynq-devcfg-1.0
15
16 reg:
17 maxItems: 1
18
19 interrupts:
20 maxItems: 1
21
22 clocks:
23 maxItems: 1
24
25 clock-names:
26 items:
27 - const: ref_clk
28
29 syscon:
30 $ref: /schemas/types.yaml#/definitions/phandle
31 description:
32 Phandle to syscon block which provide access to SLCR registers
33
34 required:
35 - compatible
36 - reg
37 - clocks
38 - clock-names
39 - syscon
40
41 additionalProperties: false
42
43 examples:
44 - |
45 devcfg: devcfg@f8007000 {
46 compatible = "xlnx,zynq-devcfg-1.0";
47 reg = <0xf8007000 0x100>;
48 interrupts = <0 8 4>;
49 clocks = <&clkc 12>;
50 clock-names = "ref_clk";
51 syscon = <&slcr>;
52 };
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