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Linux/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Broadcom STB "UPG GIO" GPIO controller
  8 
  9 description: >
 10   The controller's registers are organized as sets of eight 32-bit
 11   registers with each set controlling a bank of up to 32 pins.  A single
 12   interrupt is shared for all of the banks handled by the controller.
 13 
 14 maintainers:
 15   - Doug Berger <opendmb@gmail.com>
 16   - Florian Fainelli <f.fainelli@gmail.com>
 17 
 18 properties:
 19   compatible:
 20     items:
 21       - enum:
 22           - brcm,bcm7445-gpio
 23       - const: brcm,brcmstb-gpio
 24 
 25   reg:
 26     maxItems: 1
 27     description: >
 28       Define the base and range of the I/O address space containing
 29       the brcmstb GPIO controller registers
 30 
 31   "#gpio-cells":
 32     const: 2
 33     description: >
 34       The first cell is the pin number (within the controller's
 35       pin space), and the second is used for the following:
 36       bit[0]: polarity (0 for active-high, 1 for active-low)
 37 
 38   gpio-controller: true
 39 
 40   brcm,gpio-bank-widths:
 41     $ref: /schemas/types.yaml#/definitions/uint32-array
 42     description: >
 43       Number of GPIO lines for each bank.  Number of elements must
 44       correspond to number of banks suggested by the 'reg' property.
 45 
 46   interrupts:
 47     maxItems: 1
 48     description: >
 49       The interrupt shared by all GPIO lines for this controller.
 50 
 51   "#interrupt-cells":
 52     const: 2
 53     description: |
 54       The first cell is the GPIO number, the second should specify
 55       flags.  The following subset of flags is supported:
 56       - bits[3:0] trigger type and level flags
 57         1 = low-to-high edge triggered
 58         2 = high-to-low edge triggered
 59         4 = active high level-sensitive
 60         8 = active low level-sensitive
 61       Valid combinations are 1, 2, 3, 4, 8.
 62 
 63   interrupt-controller: true
 64 
 65   gpio-ranges: true
 66 
 67   wakeup-source:
 68     type: boolean
 69     description: >
 70       GPIOs for this controller can be used as a wakeup source
 71 
 72 required:
 73   - compatible
 74   - reg
 75   - gpio-controller
 76   - "#gpio-cells"
 77   - brcm,gpio-bank-widths
 78 
 79 additionalProperties: false
 80 
 81 examples:
 82   - |
 83     upg_gio: gpio@f040a700 {
 84         #gpio-cells = <2>;
 85         #interrupt-cells = <2>;
 86         compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
 87         gpio-controller;
 88         interrupt-controller;
 89         reg = <0xf040a700 0x80>;
 90         interrupt-parent = <&irq0_intc>;
 91         interrupts = <0x6>;
 92         brcm,gpio-bank-widths = <32 32 32 24>;
 93         gpio-ranges = <&pinctrl 0 0 120>;
 94     };
 95 
 96     upg_gio_aon: gpio@f04172c0 {
 97         #gpio-cells = <2>;
 98         #interrupt-cells = <2>;
 99         compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
100         gpio-controller;
101         interrupt-controller;
102         reg = <0xf04172c0 0x40>;
103         interrupt-parent = <&irq0_aon_intc>;
104         interrupts = <0x6>;
105         wakeup-source;
106         brcm,gpio-bank-widths = <18 4>;
107     };

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