1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: GPIO controller for Davinci and keystone devices
8
9 maintainers:
10 - Keerthy <j-keerthy@ti.com>
11
12 properties:
13 compatible:
14 oneOf:
15 - items:
16 - enum:
17 - ti,k2g-gpio
18 - ti,am654-gpio
19 - ti,j721e-gpio
20 - ti,am64-gpio
21 - const: ti,keystone-gpio
22
23 - items:
24 - enum:
25 - ti,dm6441-gpio
26 - ti,keystone-gpio
27
28 reg:
29 maxItems: 1
30
31 gpio-controller: true
32
33 gpio-ranges: true
34
35 gpio-reserved-ranges: true
36
37 gpio-line-names:
38 description: strings describing the names of each gpio line.
39 minItems: 1
40 maxItems: 144
41
42 "#gpio-cells":
43 const: 2
44 description:
45 first cell is the pin number and second cell is used to specify optional parameters (unused).
46
47 interrupts:
48 description:
49 The interrupts are specified as per the interrupt parent. Only banked
50 or unbanked IRQs are supported at a time. If the interrupts are
51 banked then provide list of interrupts corresponding to each bank, else
52 provide the list of interrupts for each gpio.
53 minItems: 1
54 maxItems: 100
55
56 ti,ngpio:
57 $ref: /schemas/types.yaml#/definitions/uint32
58 description: The number of GPIO pins supported consecutively.
59 minimum: 1
60
61 ti,davinci-gpio-unbanked:
62 $ref: /schemas/types.yaml#/definitions/uint32
63 description: The number of GPIOs that have an individual interrupt line to processor.
64 minimum: 0
65
66 clocks:
67 maxItems: 1
68
69 clock-names:
70 const: gpio
71
72 interrupt-controller: true
73
74 power-domains:
75 maxItems: 1
76
77 "#interrupt-cells":
78 const: 2
79
80 patternProperties:
81 "^(.+-hog(-[0-9]+)?)$":
82 type: object
83
84 required:
85 - gpio-hog
86
87 required:
88 - compatible
89 - reg
90 - gpio-controller
91 - "#gpio-cells"
92 - interrupts
93 - ti,ngpio
94 - ti,davinci-gpio-unbanked
95 - clocks
96 - clock-names
97
98 additionalProperties: false
99
100 examples:
101 - |
102 #include<dt-bindings/interrupt-controller/arm-gic.h>
103
104 gpio0: gpio@2603000 {
105 compatible = "ti,k2g-gpio", "ti,keystone-gpio";
106 reg = <0x02603000 0x100>;
107 gpio-controller;
108 #gpio-cells = <2>;
109 interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
110 <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
111 <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
112 <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
113 <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
114 <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
115 <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
116 <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
117 <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 ti,ngpio = <144>;
121 ti,davinci-gpio-unbanked = <0>;
122 clocks = <&k2g_clks 0x001b 0x0>;
123 clock-names = "gpio";
124 };
125
126 - |
127 #include<dt-bindings/interrupt-controller/arm-gic.h>
128
129 gpio1: gpio@260bf00 {
130 compatible = "ti,keystone-gpio";
131 reg = <0x0260bf00 0x100>;
132 gpio-controller;
133 #gpio-cells = <2>;
134 /* HW Interrupts mapped to GPIO pins */
135 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
136 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
137 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
138 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
139 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
140 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
141 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
142 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
143 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
144 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
145 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
146 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
147 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
148 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
149 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
150 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
151 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
152 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
153 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
154 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
155 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
156 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
157 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
158 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
159 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
160 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
161 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
162 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
163 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
164 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
165 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
166 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
167 clocks = <&clkgpio>;
168 clock-names = "gpio";
169 ti,ngpio = <32>;
170 ti,davinci-gpio-unbanked = <32>;
171 };
172
173 - |
174 wkup_gpio0: gpio0@42110000 {
175 compatible = "ti,am654-gpio", "ti,keystone-gpio";
176 reg = <0x42110000 0x100>;
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-parent = <&intr_wkup_gpio>;
180 interrupts = <60>, <61>, <62>, <63>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
183 ti,ngpio = <56>;
184 ti,davinci-gpio-unbanked = <0>;
185 clocks = <&k3_clks 59 0>;
186 clock-names = "gpio";
187 };
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