1 Keystone 2 DSP GPIO controller bindings
2
3 HOST OS userland running on ARM can send interrupts to DSP cores using
4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
5 This is one of the component used by the IPC mechanism used on Keystone SOCs.
6
7 For example TCI6638K2K SoC has 8 DSP GPIO controllers:
8 - 8 for C66x CorePacx CPUs 0-7
9
10 Keystone 2 DSP GPIO controller has specific features:
11 - each GPIO can be configured only as output pin;
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
14 pending.
15
16 Required Properties:
17 - compatible: should be "ti,keystone-dsp-gpio"
18 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
19 access device state control registers and the offset of device's specific
20 registers within device state control registers range.
21 - gpio-controller: Marks the device node as a gpio controller.
22 - #gpio-cells: Should be 2.
23
24 Please refer to gpio.txt in this directory for details of the common GPIO
25 bindings used by client devices.
26
27 Example:
28 dspgpio0: keystone_dsp_gpio@2620240 {
29 compatible = "ti,keystone-dsp-gpio";
30 ti,syscon-dev = <&devctrl 0x240>;
31 gpio-controller;
32 #gpio-cells = <2>;
33 };
34
35 dsp0: dsp0 {
36 compatible = "linux,rproc-user";
37 ...
38 kick-gpio = <&dspgpio0 27>;
39 };
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