1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2022 Unisoc Inc.
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/gpio/sprd,gpio.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7
8 title: Unisoc GPIO controller
9
10 maintainers:
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
14
15 description: |
16 The controller's registers are organized as sets of sixteen 16-bit
17 registers with each set controlling a bank of up to 16 pins. A single
18 interrupt is shared for all of the banks handled by the controller.
19
20 properties:
21 compatible:
22 oneOf:
23 - const: sprd,sc9860-gpio
24 - items:
25 - enum:
26 - sprd,ums512-gpio
27 - const: sprd,sc9860-gpio
28
29 reg:
30 maxItems: 1
31
32 gpio-controller: true
33
34 "#gpio-cells":
35 const: 2
36
37 interrupt-controller: true
38
39 "#interrupt-cells":
40 const: 2
41
42 interrupts:
43 maxItems: 1
44 description: The interrupt shared by all GPIO lines for this controller.
45
46 required:
47 - compatible
48 - reg
49 - gpio-controller
50 - "#gpio-cells"
51 - interrupt-controller
52 - "#interrupt-cells"
53 - interrupts
54
55 additionalProperties: false
56
57 examples:
58 - |
59 #include <dt-bindings/interrupt-controller/arm-gic.h>
60
61 soc {
62 #address-cells = <2>;
63 #size-cells = <2>;
64
65 ap_gpio: gpio@40280000 {
66 compatible = "sprd,sc9860-gpio";
67 reg = <0 0x40280000 0 0x1000>;
68 gpio-controller;
69 #gpio-cells = <2>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
72 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
73 };
74 };
75 ...
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