1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 maintainers:
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
10
11 title: NVIDIA Tegra I2C controller driver
12
13 properties:
14 compatible:
15 oneOf:
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
21 - description: Tegra20 has specific I2C controller called as DVC I2C
22 controller. This only support master mode of I2C communication.
23 Register interface/offset and interrupts handling are different than
24 generic I2C controller. Driver of DVC I2C controller is only
25 compatible with "nvidia,tegra20-i2c-dvc".
26 const: nvidia,tegra20-i2c-dvc
27 - description: |
28 Tegra30 has 5 generic I2C controller. This controller is very much
29 similar to Tegra20 I2C controller with additional feature: Continue
30 Transfer Support. This feature helps to implement M_NO_START as per
31 I2C core API transfer flags. Driver of I2C controller is compatible
32 with "nvidia,tegra30-i2c" to enable the continue transfer support.
33 This is also compatible with "nvidia,tegra20-i2c" without continue
34 transfer support.
35 items:
36 - const: nvidia,tegra30-i2c
37 - const: nvidia,tegra20-i2c
38 - description: |
39 Tegra114 has 5 generic I2C controllers. This controller is very much
40 similar to Tegra30 I2C controller with some hardware modification:
41 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
42 and fast-clk. Tegra114 has only one clock source called as
43 div-clk and hence clock mechanism is changed in I2C controller.
44 - Tegra30/Tegra20 I2C controller has enabled per packet transfer
45 by default and there is no way to disable it. Tegra114 has this
46 interrupt disable by default and SW need to enable explicitly.
47 Due to above changes, Tegra114 I2C driver makes incompatible with
48 previous hardware driver. Hence, Tegra114 I2C controller is
49 compatible with "nvidia,tegra114-i2c".
50 const: nvidia,tegra114-i2c
51 - description: |
52 Tegra124 has 6 generic I2C controllers. These controllers are very
53 similar to those found on Tegra114 but also contain several hardware
54 improvements and new registers.
55 const: nvidia,tegra124-i2c
56 - description: |
57 Tegra210 has 6 generic I2C controllers. These controllers are very
58 similar to those found on Tegra124.
59 items:
60 - const: nvidia,tegra210-i2c
61 - const: nvidia,tegra124-i2c
62 - description: |
63 Tegra210 has one I2C controller that is on host1x bus and is part of
64 the VE power domain and typically used for camera use-cases. This VI
65 I2C controller is mostly compatible with the programming model of
66 the regular I2C controllers with a few exceptions. The I2C registers
67 start at an offset of 0xc00 (instead of 0), registers are 16 bytes
68 apart (rather than 4) and the controller does not support slave
69 mode.
70 const: nvidia,tegra210-i2c-vi
71 - description: |
72 Tegra186 has 9 generic I2C controllers, two of which are in the AON
73 (always-on) partition of the SoC. All of these controllers are very
74 similar to those found on Tegra210.
75 const: nvidia,tegra186-i2c
76 - description: |
77 Tegra194 has 8 generic I2C controllers, two of which are in the AON
78 (always-on) partition of the SoC. All of these controllers are very
79 similar to those found on Tegra186. However, these controllers have
80 support for 64 KiB transactions whereas earlier chips supported no
81 more than 4 KiB per transactions.
82 const: nvidia,tegra194-i2c
83
84 reg:
85 maxItems: 1
86
87 interrupts:
88 maxItems: 1
89
90 clocks:
91 minItems: 1
92 maxItems: 2
93
94 clock-names:
95 minItems: 1
96 maxItems: 2
97
98 resets:
99 items:
100 - description: module reset
101
102 reset-names:
103 items:
104 - const: i2c
105
106 power-domains:
107 maxItems: 1
108
109 dmas:
110 items:
111 - description: DMA channel for the reception FIFO
112 - description: DMA channel for the transmission FIFO
113
114 dma-names:
115 items:
116 - const: rx
117 - const: tx
118
119 allOf:
120 - $ref: /schemas/i2c/i2c-controller.yaml
121 - if:
122 properties:
123 compatible:
124 contains:
125 enum:
126 - nvidia,tegra20-i2c
127 - nvidia,tegra30-i2c
128 then:
129 properties:
130 clocks:
131 minItems: 2
132 clock-names:
133 items:
134 - const: div-clk
135 - const: fast-clk
136
137 - if:
138 properties:
139 compatible:
140 contains:
141 enum:
142 - nvidia,tegra114-i2c
143 - nvidia,tegra210-i2c
144 then:
145 properties:
146 clocks:
147 maxItems: 1
148 clock-names:
149 items:
150 - const: div-clk
151
152 - if:
153 properties:
154 compatible:
155 contains:
156 const: nvidia,tegra210-i2c-vi
157 then:
158 properties:
159 clocks:
160 minItems: 2
161 clock-names:
162 items:
163 - const: div-clk
164 - const: slow
165 power-domains:
166 items:
167 - description: phandle to the VENC power domain
168 else:
169 properties:
170 power-domains: false
171
172 unevaluatedProperties: false
173
174 examples:
175 - |
176 i2c@7000c000 {
177 compatible = "nvidia,tegra20-i2c";
178 reg = <0x7000c000 0x100>;
179 interrupts = <0 38 0x04>;
180 clocks = <&tegra_car 12>, <&tegra_car 124>;
181 clock-names = "div-clk", "fast-clk";
182 resets = <&tegra_car 12>;
183 reset-names = "i2c";
184 dmas = <&apbdma 16>, <&apbdma 16>;
185 dma-names = "rx", "tx";
186
187 #address-cells = <1>;
188 #size-cells = <0>;
189 };
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