1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Geni based QUP I2C Controller
8
9 maintainers:
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12
13 properties:
14 compatible:
15 enum:
16 - qcom,geni-i2c
17 - qcom,geni-i2c-master-hub
18
19 clocks:
20 minItems: 1
21 maxItems: 2
22
23 clock-names:
24 minItems: 1
25 maxItems: 2
26
27 clock-frequency:
28 default: 100000
29
30 dmas:
31 maxItems: 2
32
33 dma-names:
34 items:
35 - const: tx
36 - const: rx
37
38 interconnects:
39 minItems: 2
40 maxItems: 3
41
42 interconnect-names:
43 minItems: 2
44 maxItems: 3
45
46 interrupts:
47 maxItems: 1
48
49 operating-points-v2: true
50
51 pinctrl-0: true
52 pinctrl-1: true
53
54 pinctrl-names:
55 minItems: 1
56 items:
57 - const: default
58 - const: sleep
59
60 power-domains:
61 maxItems: 1
62
63 reg:
64 maxItems: 1
65
66 required-opps:
67 maxItems: 1
68
69 required:
70 - compatible
71 - interrupts
72 - clocks
73 - clock-names
74 - reg
75
76 allOf:
77 - $ref: /schemas/i2c/i2c-controller.yaml#
78 - if:
79 properties:
80 compatible:
81 contains:
82 const: qcom,geni-i2c-master-hub
83 then:
84 properties:
85 clocks:
86 minItems: 2
87
88 clock-names:
89 items:
90 - const: se
91 - const: core
92
93 dmas: false
94 dma-names: false
95
96 interconnects:
97 maxItems: 2
98
99 interconnect-names:
100 items:
101 - const: qup-core
102 - const: qup-config
103 else:
104 properties:
105 clocks:
106 maxItems: 1
107
108 clock-names:
109 const: se
110
111 interconnects:
112 minItems: 3
113
114 interconnect-names:
115 items:
116 - const: qup-core
117 - const: qup-config
118 - const: qup-memory
119
120 unevaluatedProperties: false
121
122 examples:
123 - |
124 #include <dt-bindings/interrupt-controller/arm-gic.h>
125 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
126 #include <dt-bindings/interconnect/qcom,sc7180.h>
127 #include <dt-bindings/power/qcom-rpmpd.h>
128
129 i2c@88000 {
130 compatible = "qcom,geni-i2c";
131 reg = <0x00880000 0x4000>;
132 clock-names = "se";
133 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&qup_i2c0_default>;
136 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
140 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
141 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
142 interconnect-names = "qup-core", "qup-config", "qup-memory";
143 power-domains = <&rpmhpd SC7180_CX>;
144 required-opps = <&rpmhpd_opp_low_svs>;
145 };
146 ...
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