1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas R-Car I2C Controller
8
9 maintainers:
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
11
12 properties:
13 compatible:
14 oneOf:
15 - items:
16 - enum:
17 - renesas,i2c-r8a7778 # R-Car M1A
18 - renesas,i2c-r8a7779 # R-Car H1
19 - const: renesas,rcar-gen1-i2c # R-Car Gen1
20
21 - items:
22 - enum:
23 - renesas,i2c-r8a7742 # RZ/G1H
24 - renesas,i2c-r8a7743 # RZ/G1M
25 - renesas,i2c-r8a7744 # RZ/G1N
26 - renesas,i2c-r8a7745 # RZ/G1E
27 - renesas,i2c-r8a77470 # RZ/G1C
28 - renesas,i2c-r8a7790 # R-Car H2
29 - renesas,i2c-r8a7791 # R-Car M2-W
30 - renesas,i2c-r8a7792 # R-Car V2H
31 - renesas,i2c-r8a7793 # R-Car M2-N
32 - renesas,i2c-r8a7794 # R-Car E2
33 - const: renesas,rcar-gen2-i2c # R-Car Gen2 and RZ/G1
34
35 - items:
36 - enum:
37 - renesas,i2c-r8a774a1 # RZ/G2M
38 - renesas,i2c-r8a774b1 # RZ/G2N
39 - renesas,i2c-r8a774c0 # RZ/G2E
40 - renesas,i2c-r8a774e1 # RZ/G2H
41 - renesas,i2c-r8a7795 # R-Car H3
42 - renesas,i2c-r8a7796 # R-Car M3-W
43 - renesas,i2c-r8a77961 # R-Car M3-W+
44 - renesas,i2c-r8a77965 # R-Car M3-N
45 - renesas,i2c-r8a77970 # R-Car V3M
46 - renesas,i2c-r8a77980 # R-Car V3H
47 - renesas,i2c-r8a77990 # R-Car E3
48 - renesas,i2c-r8a77995 # R-Car D3
49 - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2
50
51 - items:
52 - enum:
53 - renesas,i2c-r8a779a0 # R-Car V3U
54 - renesas,i2c-r8a779f0 # R-Car S4-8
55 - renesas,i2c-r8a779g0 # R-Car V4H
56 - renesas,i2c-r8a779h0 # R-Car V4M
57 - const: renesas,rcar-gen4-i2c # R-Car Gen4
58
59 reg:
60 maxItems: 1
61
62 interrupts:
63 maxItems: 1
64
65 clock-frequency:
66 description:
67 Desired I2C bus clock frequency in Hz. The absence of this property
68 indicates the default frequency 100 kHz.
69
70 clocks:
71 maxItems: 1
72
73 power-domains:
74 maxItems: 1
75
76 resets:
77 maxItems: 1
78
79 dmas:
80 minItems: 2
81 maxItems: 4
82 description:
83 Must contain a list of pairs of references to DMA specifiers, one for
84 transmission, and one for reception.
85
86 dma-names:
87 minItems: 2
88 maxItems: 4
89 items:
90 enum:
91 - tx
92 - rx
93
94 i2c-scl-falling-time-ns:
95 default: 35
96 description:
97 Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
98 specification.
99
100 i2c-scl-internal-delay-ns:
101 default: 50
102 description:
103 Number of nanoseconds the IP core additionally needs to setup SCL.
104
105 i2c-scl-rising-time-ns:
106 default: 200
107 description:
108 Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
109 specification.
110
111 required:
112 - compatible
113 - reg
114 - interrupts
115 - clocks
116 - power-domains
117 - '#address-cells'
118 - '#size-cells'
119
120 allOf:
121 - $ref: /schemas/i2c/i2c-controller.yaml#
122
123 - if:
124 properties:
125 compatible:
126 contains:
127 enum:
128 - renesas,rcar-gen1-i2c
129 - renesas,rcar-gen2-i2c
130 then:
131 properties:
132 dmas: false
133 dma-names: false
134
135 - if:
136 properties:
137 compatible:
138 contains:
139 enum:
140 - renesas,rcar-gen2-i2c
141 - renesas,rcar-gen3-i2c
142 - renesas,rcar-gen4-i2c
143 then:
144 required:
145 - resets
146
147 unevaluatedProperties: false
148
149 examples:
150 - |
151 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
152 #include <dt-bindings/interrupt-controller/arm-gic.h>
153 #include <dt-bindings/power/r8a7791-sysc.h>
154
155 i2c0: i2c@e6508000 {
156 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
157 reg = <0xe6508000 0x40>;
158 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
159 clock-frequency = <400000>;
160 clocks = <&cpg CPG_MOD 931>;
161 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
162 resets = <&cpg 931>;
163 i2c-scl-internal-delay-ns = <6>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 };
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