1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/iio/resolver/adi,ad2s1210.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Analog Devices AD2S1210 Resolver-to-Digital Converter
8
9 maintainers:
10 - Michael Hennerich <michael.hennerich@analog.com>
11
12 description: |
13 The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
14 resolver-to-digital converter, integrating an on-board programmable
15 sinusoidal oscillator that provides sine wave excitation for
16 resolvers.
17
18 The AD2S1210 allows the user to read the angular position or the
19 angular velocity data directly from the parallel outputs or through
20 the serial interface.
21
22 The mode of operation of the communication channel (parallel or serial) is
23 selected by the A0 and A1 input pins. In normal mode, data is latched by
24 toggling the SAMPLE line and can then be read directly. In configuration mode,
25 data is read or written using a register access scheme (address byte with
26 read/write flag and data byte).
27
28 A1 A0 Result
29 0 0 Normal mode - position output
30 0 1 Normal mode - velocity output
31 1 0 Reserved
32 1 1 Configuration mode
33
34 In normal mode, the resolution of the digital output is selected using
35 the RES0 and RES1 input pins. In configuration mode, the resolution is
36 selected by setting the RES0 and RES1 bits in the control register.
37
38 RES1 RES0 Resolution (Bits)
39 0 0 10
40 0 1 12
41 1 0 14
42 1 1 16
43
44 Note on SPI connections: The CS line on the AD2S1210 should hard-wired to
45 logic low and the WR/FSYNC line on the AD2S1210 should be connected to the
46 SPI CSn output of the SPI controller.
47
48 Datasheet:
49 https://www.analog.com/media/en/technical-documentation/data-sheets/ad2s1210.pdf
50
51 properties:
52 compatible:
53 const: adi,ad2s1210
54
55 reg:
56 maxItems: 1
57
58 spi-max-frequency:
59 maximum: 25000000
60
61 spi-cpha: true
62
63 avdd-supply:
64 description:
65 A 4.75 to 5.25 V regulator that powers the Analog Supply Voltage (AVDD)
66 pin.
67
68 dvdd-supply:
69 description:
70 A 4.75 to 5.25 V regulator that powers the Digital Supply Voltage (DVDD)
71 pin.
72
73 vdrive-supply:
74 description:
75 A 2.3 to 5.25 V regulator that powers the Logic Power Supply Input
76 (VDrive) pin.
77
78 clocks:
79 maxItems: 1
80 description: External oscillator clock (CLKIN).
81
82 reset-gpios:
83 description:
84 GPIO connected to the /RESET pin. As the line needs to be low for the
85 reset to be active, it should be configured as GPIO_ACTIVE_LOW.
86 maxItems: 1
87
88 sample-gpios:
89 description:
90 GPIO connected to the /SAMPLE pin. As the line needs to be low to trigger
91 a sample, it should be configured as GPIO_ACTIVE_LOW.
92 maxItems: 1
93
94 mode-gpios:
95 description:
96 GPIO lines connected to the A0 and A1 pins. These pins select the data
97 transfer mode.
98 minItems: 2
99 maxItems: 2
100
101 resolution-gpios:
102 description:
103 GPIO lines connected to the RES0 and RES1 pins. These pins select the
104 resolution of the digital output. If omitted, it is assumed that the
105 RES0 and RES1 pins are hard-wired to match the assigned-resolution-bits
106 property.
107 minItems: 2
108 maxItems: 2
109
110 fault-gpios:
111 description:
112 GPIO lines connected to the LOT and DOS pins. These pins combined indicate
113 the type of fault present, if any. As these pins a pulled low to indicate
114 a fault condition, they should be configured as GPIO_ACTIVE_LOW.
115 minItems: 2
116 maxItems: 2
117
118 adi,fixed-mode:
119 description:
120 This is used to indicate the selected mode if A0 and A1 are hard-wired
121 instead of connected to GPIOS (i.e. mode-gpios is omitted).
122 $ref: /schemas/types.yaml#/definitions/string
123 enum: [config, velocity, position]
124
125 assigned-resolution-bits:
126 description:
127 Resolution of the digital output required by the application. This
128 determines the precision of the angle and/or the maximum speed that can
129 be measured. If resolution-gpios is omitted, it is assumed that RES0 and
130 RES1 are hard-wired to match this value.
131 enum: [10, 12, 14, 16]
132
133 required:
134 - compatible
135 - reg
136 - spi-cpha
137 - avdd-supply
138 - dvdd-supply
139 - vdrive-supply
140 - clocks
141 - sample-gpios
142 - assigned-resolution-bits
143
144 oneOf:
145 - required:
146 - mode-gpios
147 - required:
148 - adi,fixed-mode
149
150 allOf:
151 - $ref: /schemas/spi/spi-peripheral-props.yaml#
152
153 unevaluatedProperties: false
154
155 examples:
156 - |
157 #include <dt-bindings/gpio/gpio.h>
158
159 spi {
160 #address-cells = <1>;
161 #size-cells = <0>;
162
163 resolver@0 {
164 compatible = "adi,ad2s1210";
165 reg = <0>;
166 spi-max-frequency = <20000000>;
167 spi-cpha;
168 avdd-supply = <&avdd_regulator>;
169 dvdd-supply = <&dvdd_regulator>;
170 vdrive-supply = <&vdrive_regulator>;
171 clocks = <&ext_osc>;
172 sample-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>;
173 mode-gpios = <&gpio0 86 0>, <&gpio0 87 0>;
174 resolution-gpios = <&gpio0 88 0>, <&gpio0 89 0>;
175 assigned-resolution-bits = <16>;
176 };
177 };
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