1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
8
9 maintainers:
10 - Sibi Sankar <quic_sibis@quicinc.com>
11
12 description:
13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
15 from CPU/GPU and relays it to the OSM.
16
17 properties:
18 compatible:
19 oneOf:
20 - items:
21 - enum:
22 - qcom,sc7180-osm-l3
23 - qcom,sc8180x-osm-l3
24 - qcom,sdm670-osm-l3
25 - qcom,sdm845-osm-l3
26 - qcom,sm6350-osm-l3
27 - qcom,sm8150-osm-l3
28 - const: qcom,osm-l3
29 - items:
30 - enum:
31 - qcom,sc7280-epss-l3
32 - qcom,sc8280xp-epss-l3
33 - qcom,sm6375-cpucp-l3
34 - qcom,sm8250-epss-l3
35 - qcom,sm8350-epss-l3
36 - const: qcom,epss-l3
37
38 reg:
39 maxItems: 1
40
41 clocks:
42 items:
43 - description: xo clock
44 - description: alternate clock
45
46 clock-names:
47 items:
48 - const: xo
49 - const: alternate
50
51 '#interconnect-cells':
52 const: 1
53
54 required:
55 - compatible
56 - reg
57 - clocks
58 - clock-names
59 - '#interconnect-cells'
60
61 additionalProperties: false
62
63 examples:
64 - |
65
66 #define GPLL0 165
67 #define RPMH_CXO_CLK 0
68
69 osm_l3: interconnect@17d41000 {
70 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
71 reg = <0x17d41000 0x1400>;
72
73 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
74 clock-names = "xo", "alternate";
75
76 #interconnect-cells = <1>;
77 };
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