1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Apple Interrupt Controller 2
8
9 maintainers:
10 - Hector Martin <marcan@marcan.st>
11
12 description: |
13 The Apple Interrupt Controller 2 is a simple interrupt controller present on
14 Apple ARM SoC platforms starting with t600x (M1 Pro and Max).
15
16 It provides the following features:
17
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
23 higher priority)
24 - Automatic masking on ack
25 - Support for multiple dies
26
27 This device also represents the FIQ interrupt sources on platforms using AIC,
28 which do not go through a discrete interrupt controller. It also handles
29 FIQ-based Fast IPIs.
30
31 properties:
32 compatible:
33 items:
34 - enum:
35 - apple,t8112-aic
36 - apple,t6000-aic
37 - const: apple,aic2
38
39 interrupt-controller: true
40
41 '#interrupt-cells':
42 minimum: 3
43 maximum: 4
44 description: |
45 The 1st cell contains the interrupt type:
46 - 0: Hardware IRQ
47 - 1: FIQ
48
49 The 2nd cell contains the die ID (only present on apple,t6000-aic).
50
51 The next cell contains the interrupt number.
52 - HW IRQs: interrupt number
53 - FIQs:
54 - 0: physical HV timer
55 - 1: virtual HV timer
56 - 2: physical guest timer
57 - 3: virtual guest timer
58
59 The last cell contains the interrupt flags. This is normally
60 IRQ_TYPE_LEVEL_HIGH (4).
61
62 reg:
63 items:
64 - description: Address and size of the main AIC2 registers.
65 - description: Address and size of the AIC2 Event register.
66
67 reg-names:
68 items:
69 - const: core
70 - const: event
71
72 power-domains:
73 maxItems: 1
74
75 affinities:
76 type: object
77 additionalProperties: false
78 description:
79 FIQ affinity can be expressed as a single "affinities" node,
80 containing a set of sub-nodes, one per FIQ with a non-default
81 affinity.
82 patternProperties:
83 "^.+-affinity$":
84 type: object
85 additionalProperties: false
86 properties:
87 apple,fiq-index:
88 description:
89 The interrupt number specified as a FIQ, and for which
90 the affinity is not the default.
91 $ref: /schemas/types.yaml#/definitions/uint32
92 maximum: 5
93
94 cpus:
95 $ref: /schemas/types.yaml#/definitions/phandle-array
96 description:
97 Should be a list of phandles to CPU nodes (as described in
98 Documentation/devicetree/bindings/arm/cpus.yaml).
99
100 required:
101 - apple,fiq-index
102 - cpus
103
104 required:
105 - compatible
106 - '#interrupt-cells'
107 - interrupt-controller
108 - reg
109 - reg-names
110
111 additionalProperties: false
112
113 allOf:
114 - $ref: /schemas/interrupt-controller.yaml#
115 - if:
116 properties:
117 compatible:
118 contains:
119 const: apple,t8112-aic
120 then:
121 properties:
122 '#interrupt-cells':
123 const: 3
124 else:
125 properties:
126 '#interrupt-cells':
127 const: 4
128
129 examples:
130 - |
131 soc {
132 #address-cells = <2>;
133 #size-cells = <2>;
134
135 aic: interrupt-controller@28e100000 {
136 compatible = "apple,t6000-aic", "apple,aic2";
137 #interrupt-cells = <4>;
138 interrupt-controller;
139 reg = <0x2 0x8e100000 0x0 0xc000>,
140 <0x2 0x8e10c000 0x0 0x4>;
141 reg-names = "core", "event";
142 };
143 };
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