1 * ARM Nested Vector Interrupt Controller (NVIC)
2
3 The NVIC provides an interrupt controller that is tightly coupled to
4 Cortex-M based processor cores. The NVIC implemented on different SoCs
5 vary in the number of interrupts and priority bits per interrupt.
6
7 Main node required properties:
8
9 - compatible : should be one of:
10 "arm,v6m-nvic"
11 "arm,v7m-nvic"
12 "arm,v8m-nvic"
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
15 interrupt source. The type shall be a <u32> and the value shall be 2.
16
17 The 1st cell contains the interrupt number for the interrupt type.
18
19 The 2nd cell is the priority of the interrupt.
20
21 - reg : Specifies base physical address(s) and size of the NVIC registers.
22 This is at a fixed address (0xe000e100) and size (0xc00).
23
24 - arm,num-irq-priority-bits: The number of priority bits implemented by the
25 given SoC
26
27 Example:
28
29 intc: interrupt-controller@e000e100 {
30 compatible = "arm,v7m-nvic";
31 #interrupt-cells = <2>;
32 #address-cells = <1>;
33 interrupt-controller;
34 reg = <0xe000e100 0xc00>;
35 arm,num-irq-priority-bits = <4>;
36 };
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