1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
2
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
5 controller, or the HW block containing it, is referred to occasionally
6 as "armctrl" in the SoC documentation, hence naming of this binding.
7
8 The BCM2836 contains the same interrupt controller with the same
9 interrupts, but the per-CPU interrupt controller is the root, and an
10 interrupt there indicates that the ARMCTRL has an interrupt to handle.
11
12 Required properties:
13
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15 "brcm,bcm2836-armctrl-ic"
16 - reg : Specifies base physical address and size of the registers.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
19 interrupt source. The value shall be 2.
20
21 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
22 pending" register, or 1/2 respectively for interrupts in the "IRQ pending
23 1/2" register.
24
25 The 2nd cell contains the interrupt number within the bank. Valid values
26 are 0..7 for bank 0, and 0..31 for bank 1.
27
28 Additional required properties for brcm,bcm2836-armctrl-ic:
29 - interrupts : Specifies the interrupt on the parent for this interrupt
30 controller to handle.
31
32 The interrupt sources are as follows:
33
34 Bank 0:
35 0: ARM_TIMER
36 1: ARM_MAILBOX
37 2: ARM_DOORBELL_0
38 3: ARM_DOORBELL_1
39 4: VPU0_HALTED
40 5: VPU1_HALTED
41 6: ILLEGAL_TYPE0
42 7: ILLEGAL_TYPE1
43
44 Bank 1:
45 0: TIMER0
46 1: TIMER1
47 2: TIMER2
48 3: TIMER3
49 4: CODEC0
50 5: CODEC1
51 6: CODEC2
52 7: VC_JPEG
53 8: ISP
54 9: VC_USB
55 10: VC_3D
56 11: TRANSPOSER
57 12: MULTICORESYNC0
58 13: MULTICORESYNC1
59 14: MULTICORESYNC2
60 15: MULTICORESYNC3
61 16: DMA0
62 17: DMA1
63 18: VC_DMA2
64 19: VC_DMA3
65 20: DMA4
66 21: DMA5
67 22: DMA6
68 23: DMA7
69 24: DMA8
70 25: DMA9
71 26: DMA10
72 27: DMA11-14 - shared interrupt for DMA 11 to 14
73 28: DMAALL - triggers on all dma interrupts (including channel 15)
74 29: AUX
75 30: ARM
76 31: VPUDMA
77
78 Bank 2:
79 0: HOSTPORT
80 1: VIDEOSCALER
81 2: CCP2TX
82 3: SDC
83 4: DSI0
84 5: AVE
85 6: CAM0
86 7: CAM1
87 8: HDMI0
88 9: HDMI1
89 10: PIXELVALVE1
90 11: I2CSPISLV
91 12: DSI1
92 13: PWA0
93 14: PWA1
94 15: CPR
95 16: SMI
96 17: GPIO0
97 18: GPIO1
98 19: GPIO2
99 20: GPIO3
100 21: VC_I2C
101 22: VC_SPI
102 23: VC_I2SPCM
103 24: VC_SDIO
104 25: VC_UART
105 26: SLIMBUS
106 27: VEC
107 28: CPG
108 29: RNG
109 30: VC_ARASANSDIO
110 31: AVSPMON
111
112 Example:
113
114 /* BCM2835, first level */
115 intc: interrupt-controller {
116 compatible = "brcm,bcm2835-armctrl-ic";
117 reg = <0x7e00b200 0x200>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 };
121
122 /* BCM2836, second level */
123 intc: interrupt-controller {
124 compatible = "brcm,bcm2836-armctrl-ic";
125 reg = <0x7e00b200 0x200>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
128
129 interrupt-parent = <&local_intc>;
130 interrupts = <8>;
131 };
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